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News - Technologies, procédés, découvertes, actualité et situation

n°8035469
super_newb​ie_pro
A ta dispoition frère geek :P
Posté le 07-09-2011 à 13:36:37  profilanswer
 
mood
Publicité
Posté le 07-09-2011 à 13:36:37  profilanswer
 

n°8037376
super_newb​ie_pro
A ta dispoition frère geek :P
Posté le 08-09-2011 à 23:39:56  profilanswer
 

Jusqu’à cent couches de silicium les unes sur les autres
 
3M et IBM ont annoncé vouloir développer une substance adhésive qui permettrait d’empiler jusqu’à cent couches de silicium les unes sur les autres. IBM envisage la création de puces 3D pour des architectures complexes, comme celles des microprocesseurs. Le projet est très ambitieux, mais personne ne donne pour l’instant de date de commercialisation.
 
IBM apportera son expertise dans la fabrication de semi-conducteurs et de packagings. 3M se concentrera sur le matériau adhésif. Comme le montre la vidéo ci-dessous, le but est d’offrir une colle capable de soutenir le die en silicium et dissiper la chaleur, ce qui est loin d’être facile.
Quid des interconnexions
 
Le communiqué de Big Blue oublie néanmoins une question importante qui est celle des interconnexions. C’est pourtant un problème important et épineux. Les puces qui peuvent aujourd’hui empiler plusieurs dies les uns sur les autres sont très souvent des puces mémoires, car leur architecture est suffisamment simple pour permettre ce genre de manoeuvre. Très souvent, les fondeurs utilisent le TSV (Through Silicon Via), un procédé qui fait traverser les interconnexions dans le die pour relier les divers étages. Il est aussi possible de placer les interconnexions à l’extérieur du die, mais il est reconnu que c’est une solution moins optimale que le TSV qui permet des liens plus courts et plus ordonnés. La vidéo laisse penser à une structure TSV. Nous avons contacté IBM et attendons une réponse de leur part à ce sujet. Nous mettrons cette actualité à jour dès que nous aurons plus d’information.
Pas avant dix ans
 
Si IBM arrive à tenir ses promesses et à empiler les cores d’un microprocesseur, ce serait une révolution majeure dans le domaine des semi-conducteurs. En effet, plus un die a une surface importante et plus il est difficile à fabriquer et donc plus cher. En empilant des dies de plus petites surfaces, il est possible de réduire les coûts de production en ne rejetant que les dies défectueux et non l’ensemble de la puce. Il est aussi possible d’intégrer plus de composants dans un seul packaging. L’idée est très alléchante, mais nous ne pensons pas voir un microprocesseur à 100 étages avant au moins dix ans.
 
La vidéo : http://youtu.be/rbj5vrXulD0
 
source ; http://www.presence-pc.com/actuali [...] sif-44896/


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~ Sondage sur un lieu d'apprentissage de l'autonomisme ~ Camping la ressource ; Le survivalisme accessible ~
n°8040945
gliterr
Posté le 12-09-2011 à 11:29:16  profilanswer
 

Semiconductor Rumors: 14nm Node and 450mm Wafers by 2015
http://www.brightsideofnews.com/ne [...] -2015.aspx
 
http://www.brightsideofnews.com/Data/2011_9_11/Rumors-14nm-node-and-450mm-wafers-by-2015/GlobalFoundries_Beyond_20nm.jpg
 
Des infos sur SOITEC egalement et l'evolution vers les waffer en 450mm


Message édité par gliterr le 12-09-2011 à 11:30:37
n°8045723
super_newb​ie_pro
A ta dispoition frère geek :P
Posté le 16-09-2011 à 00:37:08  profilanswer
 

TSMC thinks 14nm by 2015
You have to wonder at what point they can't make it any smaller right ? TSMC R&D head Shang-yi Chiang said volume production of 14nm chips is expected to happen in 2015. Additionally, he also reveals this process node will use 450mm wafers:
 
Taiwan Semiconductor Manufacturing Company (TSMC) will conduct R&D for 14nm process technology starting 2012, and expects to begin volume production on the node in 2015, according to Shang-yi Chiang, company senior VP of R&D. TSMC will use 18-inch wafers to process 14nm chips, said Chiang, adding that manufacturing with larger wafers helps increase its ability to produce at a lower cost.
 
The transition to larger, 18-inch-sized wafers will also allow TSMC to build fewer fabs, meaning that labor and land costs can be reduced, Chiang pointed out. In its ongoing advanced technology development, TSMC is actually facing a shortage of engineers rather than technical issues, Chiang added.
 
http://www.guru3d.com/news/tsmc-thinks-14nm-by-2015/
 
Bon comme c'est TSMC, on va dire que ça sera un an de retard et donc pour 2016...(...)


---------------
~ Sondage sur un lieu d'apprentissage de l'autonomisme ~ Camping la ressource ; Le survivalisme accessible ~
n°8046738
Invite_Sur​prise
Racaille de Shanghaï
Posté le 16-09-2011 à 23:47:46  profilanswer
 

Ultra boards for ultrabooks - EETimes
 

Citation :

Panasonic showed at IDF two novel printed circuit boards, geared to be great ingredients for ultrabooks--thin and light notebook PCs that aim to imitate the Apple Mac Air. It is now shipping a pcb (top) that can embedded die into the board's surface to help keep chassis razor thin. Meanwhile it is also developing a flexible board technology (bottom) that will support six layers.


 
http://tof.canardpc.com/view/83053945-d527-464f-822e-78c84c3d0453.jpg
 
http://tof.canardpc.com/view/5c83caa6-e6b7-4210-882a-a65c7feb350e.jpg

n°8060211
Silicium77​7
Lurkeur compulsif
Posté le 28-09-2011 à 12:09:38  profilanswer
 

X-post :o
 
Intel, IBM, Globalfoundries, TSMC & Samsung s'accocient dans un centre de R&D à New York pour mettre en place la gravure sur galettes de silicium de 450 mm.
Simultanément IBM, Global Foundries & Samsung confirment leur alliance pour mettre en place les procédés de gravure en 22 & 14 nm.  
L'investissement totalisera 4,4 milliards de $.
 
[:b-net] Intel, IBM to lead $4.4B chip R&D hub in NY

n°8095865
Invite_Sur​prise
Racaille de Shanghaï
Posté le 26-10-2011 à 18:00:35  profilanswer
 

TSMC's R&D chief sees 10 years of scaling - EETimes
 

Citation :

The path is clear for continued semiconductor scaling using FinFETs for the next decade, down to the 7-nm node, according to Shang-Yi Chiang, senior vice president of R&D at foundry giant Taiwan Semiconductor Manufacturing Co.
Beyond 7-nm, the most pressing challenges to continued scaling will come from economics, not technology, Chiang said in a keynote address at the ARM TechCon event here Tuesday (Oct. 25).


 

Citation :

At the 32-nm node, a chip needs to sell about 30 to 40 million units to recoup the costs associated with it, Hsu said. At the 20-nm node, the "breakeven" point jumps to between 60 and 100 million units, Hsu said.


 

Citation :

Chiang said the 20-nm node will be the last generation at which the semiconductor industry can possibly use a planar transistor. "After that, it will run out of steam," Chiang said.

n°8097596
Invite_Sur​prise
Racaille de Shanghaï
Posté le 28-10-2011 à 00:31:39  profilanswer
 

ARM aims for the server room with its new 64-bit ARMv8 architecture - Ars Technica
 

Citation :

Chip design firm ARM today announced the eighth generation of its ARM Instruction Set Architecture (ISA). The ARMv8 ISA extends the current ARMv7 architecture to include support for 64-bit addressing. The company said that this move would enable the architecture to be used in servers and other enterprise roles, bringing ARM's low-power advantage to a market that's increasingly challenged by power consumption and energy efficiency.


 

Citation :

Hardware designers will have to wait a little longer. ARM plans to release the first chip designs that support ARMv8 next year, and expects prototype systems using these designs to emerge in 2014. One early customer of the designs is likely to be Hewlett-Packard: Bloomberg is reporting claims that the company is planning to ship ARM servers.

n°8102543
Fouge
Posté le 01-11-2011 à 10:46:43  profilanswer
 

Les transistors en graphène se rapprochent

Citation :

Deux papiers publiés dans la revue Nature Physics de ce mois-ci permettent d’envisager la fabrication de transistors en graphène à trois couches et si nous sommes encore loin de leur commercialisation, il est indéniable que la recherche avance à grands pas.

n°8110096
Invite_Sur​prise
Racaille de Shanghaï
Posté le 07-11-2011 à 12:03:56  profilanswer
 
mood
Publicité
Posté le 07-11-2011 à 12:03:56  profilanswer
 

n°8150447
gliterr
Posté le 15-12-2011 à 13:07:44  profilanswer
 

http://semiaccurate.com/2011/12/14 [...] does-20nm/
 
Puce ARM A9 tape-out en 20nm chez GF.

n°8161135
Invite_Sur​prise
Racaille de Shanghaï
Posté le 23-12-2011 à 20:05:54  profilanswer
 

TSMC to enter volume production on 18-inch wafers as early as 2015 - Digitimes
 

Citation :

Taiwan Semiconductor Manufacturing Company (TSMC) will maintain its plans to begin trial production on 18-inch wafers in the 2013-2014 timeframe, with volume production slated for 2015-16, according to the foundry chipmaker.
 
TSMC expects to have about 95% of its 18-inch produciton equipment and facilities installed in 2014, and start small-volume production on the larger wafers in 2015. Currently, the move to 18-inch wafers still faces technical barriers that have to be solved in collaboration with equipment and material suppliers, TSMC pointed out.
 
Without support from makers of equipment and materials, no foundry can build and ramp 18-inch product lines on its own, TSMC claimed.
 
The transition to 18-inch wafer production is aimed at creating more powerful chips, and also enabling a more cost-effective manufacturing method, TSMC said. It is not just having larger wafers, but adding more value to customer products.
 
TSMC previously revealed plans to conduct R&D for 14nm process technology starting 2012, and begin volume production on the node in 2015. It would use 18-inch wafers to process 14nm chips, the foundry noted.

n°8184144
Swiss_Knig​ht
600 MeV since 1957.
Posté le 11-01-2012 à 17:45:32  profilanswer
 

C'était passé ça ?
http://actu.epfl.ch/news/premiere- [...] lybdenite/

Citation :

"Après avoir mis les vertus électroniques de la molybdénite en lumière, des chercheurs de l’EPFL font le pas décisif suivant. Le Laboratoire d'électronique et structures à l'échelle nanométrique (LANES) a réussi à créer un circuit intégré avec des transistors composés de ce minéral. Un essai qui confirme que ce nouveau matériau peut dépasser les limites physiques du silicium en matière de miniaturisation, de consommation et de souplesse mécanique."


---------------
Hergestellt in der Schweiz.
n°8202242
Wirmish
¡sıɹdɹns zǝɹǝs snoʌ
Posté le 29-01-2012 à 19:48:14  profilanswer
 

Maintenant ça l'est. ;)

n°8202752
Invite_Sur​prise
Racaille de Shanghaï
Posté le 30-01-2012 à 12:07:04  profilanswer
 

IBM, un transistor de 9 nm en nanotube de carbone - Tom's Hardware
 

Citation :

IBM vient de montrer pour la première fois un transistor dont le canal entre la source et le drain est composé d’un nanotube de carbone de seulement 9 nm de longueur. Il est extrêmement petit et dispose de performances dépassant celles des modèles en silicium à taille égale.


 
http://tof.canardpc.com/view/cc65cbe1-fc42-4cbb-b22c-7b6cbf2e9c3c.jpg http://tof.canardpc.com/view/9646064a-f3ea-47af-8bc8-f8697302db7e.jpg

n°8202799
Profil sup​primé
Posté le 30-01-2012 à 13:04:57  answer
 

Drap !

n°8208253
Wirmish
¡sıɹdɹns zǝɹǝs snoʌ
Posté le 04-02-2012 à 16:27:56  profilanswer
 

Citation :

Des chercheurs de l’École polytechnique fédérale de Lausanne (Suisse) ont créé des circuits d’une finesse de moins d’un nanomètre. Une taille que ne pourra jamais atteindre le silicium. Et pour cause, pour parvenir à cette prouesse, ils ont employé du molybdène, une substance qui ressemble au graphène, avec toutefois un atout supplémentaire. Bon marché, la molybdénite est disponible en grande quantité dans la nature, ce qui tombe bien pour les chercheurs, puisque la région du Valais, en Suisse, en regorge.
 
La limite ultime du silicium, cependant, commence à approcher, et se situerait autour de 10 nanomètres. Avec la molybdénite, il serait possible, affirme l'équipe de l'EPFL, d'atteindre des finesses de 3 ou 4 nanomètres à l'échelle industrielle. Autre avantage : une consommation électrique bien inférieure à celle des puces à base de silicium.  
 
Lors des tests, les chercheurs suisses ont déposé sur une plaque de silicium une feuille de molybdénite de 0,65 nanomètre d'épaisseur pour la transformer en transistor. Avec cette finesse, les performances ont été surprenantes : 800 cm² par volt-seconde, au lieu des 200 cm²/Vs que conférerait un circuit de silicium de 2 nanomètres.
 
http://www.extremetech.com/wp-content/uploads/2012/01/moly1-300x225.jpg
 
Pas de quoi faire trembler les adeptes du graphène qui parviennent à réaliser leurs expérimentations avec la même finesse. Mais ce matériau souffre d’un lourd handicap. Il ne dispose pas d’un « gap » suffisant. Ce « gap » est une caractéristique essentielle pour les semi-conducteurs. Il indique leur capacité à assurer la conduction électrique en fonction de la tension délivrée. C’est justement sur cette carence du graphène que des scientifiques du monde entier travaillent. Andras Kis confirme cette lacune en ajoutant que « même IBM, a récemment admis qu’il n’est pas préférable de remplacer le silicium par le graphène ».  
 
À la différence du graphène, la molybdénite dispose d’un excellent gap ! Un atout qui fait vraiment la différence et pourrait mettre un terme aux espoirs investis dans le graphène en électronique.


Alors, le futur des transistors sera en carbone, en graphène, ou en molybdénite ?

n°8223172
Invite_Sur​prise
Racaille de Shanghaï
Posté le 21-02-2012 à 14:25:39  profilanswer
 

Intel confirmed as foundry for second FPGA startup - EETimes
 

Citation :

Programmable logic startup Tabula Inc. confirmed Tuesday (Feb. 21) that Intel Corp. will manufacture the firm's 22-nm 3PLD products using Intel's 3-D tri-gate transistors.
 
Tabula (Santa Clara, Calif.) becomes the second programmable logic startup confirmed to be using Intel's Custom Foundry division for foundry work. In October 2010, Achronix Semiconductor Corp. announced that Intel would build its 22-nm FPGAs.

n°8226868
Invite_Sur​prise
Racaille de Shanghaï
Posté le 25-02-2012 à 00:24:13  profilanswer
 

Globalfoundries to acquire ProMOS for NT$20-30 billion, say sources - Digitimes
 

Citation :

Globalfoundries reportedly has agreed to take over financially-troubled ProMOS Technologies for NT$20-30 billion (US$0.7-1 billion), according to industry sources. By adding ProMOS' 12-inch wafer fab in Taichung, central Taiwan to its global manufacturing facilities, Globalfoundries will be striving for orders from IC design houses in China and Taiwan, the sources indicated.


 

Citation :

According to Digitimes Research, industry leader TSMC expanded its market share to 55% in the fourth quarter of 2011, followed by UMC with 13%. Globalfoundries trailed close behind UMC with 12% during the period.

n°8237799
Invite_Sur​prise
Racaille de Shanghaï
Posté le 07-03-2012 à 15:08:00  profilanswer
 

AMD Ditches SOI : Kaveri goes Bulk at GF, More Details From the New WSA - BSN*
 

Citation :

"We said that at the 28nm node we are going to be on bulk silicon across all products, not only graphics but also CPUs. And We have made no statement beyond that. But for 28[nm] we will be on bulk for all products. Thomas Seifert CFO AMD"


 

Citation :

While technically he hasn't denied the use of SOI going forward, for example at the 22nm node, at this point it seems a bit unlikely. Once you have transitioned your entire product lineup to a bulk process you are not going to move back to SOI at the next half-node step again, unless there are significant benefits to do so. The statement regarding the increased flexibility at a bulk process are a strong hint that going forward AMD would rather avoid SOI.

n°8250651
gliterr
Posté le 20-03-2012 à 12:08:36  profilanswer
 

http://semiaccurate.com/2012/03/19 [...] 4nm-wafer/
 
IBM was the first to show off 14nm wafers at Common Platform last week, and they are pretty. If you haven’t been following the tech lately, this is the first non-Intel FinFET to be publicly shown off. No specs were given, nor was the chip itself identified, but it is almost assuredly a test part.

n°8278603
Invite_Sur​prise
Racaille de Shanghaï
Posté le 16-04-2012 à 09:16:26  profilanswer
 

Nvidia calls for move to 450mm wafers - EETimes
 

Citation :

The industry needs to move to 450mm wafers to deal with the increasing number of masks and process steps required to make chips, he told EE Times in a discussion before the keynote. The larger wafers would spread the costs out among more chips and reduce the processing time per chip, he said.
 
However, Halapete said he is not seeing any signs the shift to the larger wafers will come in time for the 14nm process node. That’s the next big jump after the 28nm chips Nvidia and others are just starting to deliver.


 

Citation :

“Between the 40 and 28nm nodes it lengthened by maybe four to six weeks” due to more masks and process steps he said.
 
Getting to volume production can now take as much as three months longer than in past generations, he said. “But the Christmas and back-to-school selling seasons are not going to move for you,” he quipped.


 

Citation :

New process technologies are “running out of steam” in their ability to lower power because voltages are not decreasing significantly, he said. Thus the next wave of improvements in energy efficiency will come from tools that can suggest optimizations in logic and circuit designs.


n°8312793
Invite_Sur​prise
Racaille de Shanghaï
Posté le 13-05-2012 à 23:52:10  profilanswer
 
n°8321568
Wirmish
¡sıɹdɹns zǝɹǝs snoʌ
Posté le 21-05-2012 à 17:13:13  profilanswer
 

New memristor offers super-fast memory
 

Citation :

"Our ReRAM memory chips need just a thousandth of the energy and are around a hundred times faster than standard Flash memory chips," says UCL's Dr Tony Kenyon.

n°8322125
Wirmish
¡sıɹdɹns zǝɹǝs snoʌ
Posté le 22-05-2012 à 02:34:24  profilanswer
 


Soitec: Wafer Roadmap for Fully Depleted Planar and 3D/FinFET
 

Citation :

Compared to using conventional bulk silicon starting wafers, our FD-3D wafers result in fewer challenging steps in the FinFET fabrication process, driving lower capital expenditures and operating expenses, higher production throughput and ultimately lower cost. Typical savings include four lithography steps and over 55 process steps.

Citation :

At 28nm, compared to conventional technology, the energy consumption of chips built on our FD-2D wafers can be reduced by up to 40 percent, and the maximum operating frequency of the processors these chips embed can be improved by 40 percent or more with design optimizations.

http://www.advancedsubstratenews.com/wp-content/uploads/2012/04/soitec_fig3.png
 
http://www.advancedsubstratenews.com/wp-content/uploads/2012/04/soitec_fig4.png

n°8379886
Wirmish
¡sıɹdɹns zǝɹǝs snoʌ
Posté le 12-07-2012 à 23:58:45  profilanswer
 
n°8449959
Invite_Sur​prise
Racaille de Shanghaï
Posté le 14-09-2012 à 22:58:00  profilanswer
 

Intel : We know how to make 10nm chips -ZDNet
 
http://tof.canardpc.com/view/8ab43b94-da33-4317-a679-a44617385cef.jpg
 

Citation :

The 14nm technology is in full development mode now and on track for full production readiness at the end of next year," Mark Bohr, director of process architecture and integration for Intel's technology manufacturing group, said. "Right now I'm spending my time personally on 10nm pathfinding and it looks like we have a solution there.


 

Citation :

When it comes to how the 10nm chips will be manufactured, Intel has an immersion lithography method that works, though it would prefer to use EUV.
I'd like to have EUV for 10, but I can't bet that it would be ready in time," Bohr said, hinting at the difficulties in using this method. EUV has much higher costs than immersion lithography.


 

Citation :

Intel's research group are also exploring technologies for 7nm and 5nm solutions, though these are a very long way off as 10nm is not expected to go into production qualification until 2015.

n°8514662
Invite_Sur​prise
Racaille de Shanghaï
Posté le 15-11-2012 à 13:12:43  profilanswer
 

Samsung Begins Production of 64GB eMMC Storage Solutions Using 10nm-Class Process Technology - XBitLabs
 

Citation :

Samsung Electronics said this week that its new 64Gb eMMC NAND flash memory storage chip for smartphones and tablets memory went into production late last month using 10nm-class process technology.


 

Citation :

The new eMMC 64GB Pro 2000 memory solution has a random write speed of 2000 IOPS (input/output per second) and a random read speed of 5000 IOPS. In addition, sequential read and write speeds are 260MB/s and 50MB/s respectively, which is up to 10 times faster than a class 10 external memory card that reads at 24MB/s and writes at 12MB/s, greatly enhancing the smoothness of multitasking on mobile gadgets.


 
http://tof.canardpc.com/view/0fa85d7c-cbff-44b5-9064-f61ebf7fcca5.jpg
 
edit : 10-nm class signifie - de 20nm. Attention donc.


Message édité par Invite_Surprise le 16-11-2012 à 15:27:19
n°8556337
Invite_Sur​prise
Racaille de Shanghaï
Posté le 21-12-2012 à 14:20:56  profilanswer
 

Samsung 14-nm FinFET test chip pushes ecosystem - EETimes
 

Citation :

The Korean chip maker, leveraging a team including ARM, Cadence, Mentor Graphics and Synopsys, announced Thursday (Dec. 20) that it has taped out multiple test chips ranging from a full ARM Cortex A7 processor implementation (using the low-power component of the ARM's "big-little" processor configuration/technology) to a SRAM-based chip capable of operation near threshold voltage levels as well as an array of analog IP.
 
The announcement was the second notable 14-nm FinFET achievement in a month.  
In November, Cadence announced the tapeout of a 14-nanometer test-chip featuring an ARM Cortex-M0 processor implemented using IBM's FinFET process technology.


 
http://www.cadence.com/cadence/new [...] T&CMP=home

n°8558712
Invite_Sur​prise
Racaille de Shanghaï
Posté le 24-12-2012 à 01:34:41  profilanswer
 

A Review of TSMC 28 nm Process Technology - Chipworks
 

Citation :

TSMC’s 28 nm CMOS technology platform is currently their most advanced offering. Our analysis suggests that this will be a very profitable technology platform for TSMC and for their fabless design partners for many years to come. In fact, Chairman Morris Chang expects that 28 nm will be the biggest node ever, exceeding the 65 nm node in production volumes, with more than 130,000 wafers per month at the peak.


 
http://tof.canardpc.com/view/78560eda-8892-4bf6-8641-72cc2330f437.jpg http://tof.canardpc.com/view/e46ac941-6b04-4b29-8acf-2379c4527259.jpg

n°8688042
Invite_Sur​prise
Racaille de Shanghaï
Posté le 13-04-2013 à 11:51:29  profilanswer
 

TSMC starts FinFETs in 2013, tries EUV at 10 nm - EETimes
 

Citation :

Sun also said 20-nm chips could sport 20 percent higher speeds or 30 percent less power consumption than 28-nm ones [...] TSMC expects to have about 20 tapeouts at the 20-nm node this year at its fab 12 and 14 plants. Mass production at that node really starts in 2014, said Wang [...] TSMC expects silicon back in May on a 20-nm test device based on an ARM Cortex A15 core, Hou said.


 

Citation :

“We are confident the 16 FinFET process will be there for prime time [production] next year,” said Sun.
TSMC showed a chart estimating a 64-bit ARM core in the 16-nm node will have 90 percent greater performance than a 32-bit ARM A9 core in 28 nm. By contrast an ARM A15 in the 20-nm node will give about a 40 percent boost, TSMC estimated.


 

Citation :

If all goes well, the 10nm node could offer another 90 percent increase in gate level density. It could also deliver 35 percent speed ups at the same power or 40 percent in power savings at the same speed as a 16nm device, Sun estimated.


 

Citation :

TSMC estimates all the tools will be ready for high-volume production by the end of 2015 -- except the litho systems. Immersion systems won’t be ready for 450-mm wafers until late 2017, and EUV…well, Wang hopes they could be ready at the start of 2018. Again the key word is “hopes.”
So, TSMC plans to start a pilot 450-mm wafer line in 2016 or 2017, ramping production of 10 or 7-nm chips.


 
http://tof.canardpc.com/view/9e54259f-3829-4136-8a04-4011c1f31f46.jpg
 
450mm/300mm

n°8847006
Invite_Sur​prise
Racaille de Shanghaï
Posté le 30-08-2013 à 13:10:34  profilanswer
 

Samsung Now Mass Producing Industry’s Most Advanced DDR4, Using 20 Nanometer-class Process Technology
 
http://tof.canardpc.com/preview2/18a92529-bb47-4c61-92be-e474964abe5f.jpg
 

Citation :

With the introduction of these high-performance, high-density DDR4 modules, Samsung can better support the need for advanced DDR4 in rapidly expanding, large-scale data centers and other enterprise server applications.
 
Early market availability of the 4-gigabit (Gb) DDR4 devices, which use 20 nanometer (nm)-class* process technology, will facilitate demand for 16-gigabyte (GB) and 32GB memory modules. This compares to conventional DRAM of which 8GB modules using a 30nm-class* process technology are still commonplace.


 

Citation :

Editors’ Note: 20 nm-class means a process technology node somewhere between 20 and 30 nanometers, 30 nm-class means a process technology node somewhere between 30 and 40 nanometers, and 50 nm-class means a process technology node somewhere between 50 and 60 nanometers.

n°8867693
gliterr
Posté le 19-09-2013 à 00:14:21  profilanswer
 

http://www.xbitlabs.com/news/other [...] Flows.html
 
TSMC Delivers 16FinFET and 3D IC Reference Flows.

TSMC and EDA Vendors Unleash Three 16nm Reference Flows
 
Il semble par contre, que comme pour les process "14" ou "16nm" à venir chez GloFo ou STM, il s'agit plus de 20nm.

n°9015561
gliterr
Posté le 15-01-2014 à 10:08:28  profilanswer
 

Enfin, des informations sur la presentation de STMicroelectronics, CEA-LETI, IBM, Renesas, SOITEC et GLOBALFOUNDRIES au dernier IEDM sur le process FD-SOI en "14nm".
Les parentheses sont la pour rappeler que la densite devrait etre plus proche d'un procede en 20nm.
 
https://www.semiwiki.com/forum/cont [...] ength.html
 
Je ne serais pas contre l'avis d'experts en ce domaine vu qu'a titre personnel, je suis rapidement depasse.

n°9069166
Invite_Sur​prise
Racaille de Shanghaï
Posté le 25-02-2014 à 21:16:22  profilanswer
 

First tape-out with TSMC’s 16nm FinFET and ARM’s 64-bit big.LITTLE Processors - ARM
 

Citation :

Another important milestone was reached recently for TSMC  and ARM when the teams taped out at the end of December 2013 (see block diagram) the first 64 bit ARMv8 processors in a big.LITTLE configuration on TSMC’s leading edge manufacturing process, 16nm FinFET.


 

Citation :

As previously announced in January, TSMC will have more than 20 customer tape-outs in 16FinFET during 2014


 

Citation :

Innovation is continuing at TSMC with the development of enhanced 16nm FinFET (16FF+) process that will offer an additional 15% performance improvement with no power or area penalty.

n°9149214
gliterr
Posté le 14-05-2014 à 20:04:13  profilanswer
 

C'est Montbourg qui va etre content :)

 

STMicro décroche un accord avec Samsung sur une technologie clef

 


Samsung, deuxième fabricant mondial de semi-conducteurs derrière Intel, va pouvoir utiliser la plate-forme technologique de silicium sur isolant dite "FD-SOI" ("Fully Depleted Silicon on Insulator" ) de 28 nanomètres conçue dans un pôle de recherche à Grenoble par le Commissariat à l'énergie atomique (CEA) et par l'entreprise Soitec.

 

Un petit PDF pour illustrer:
http://www.semiwiki.com/forum/file [...] FINAL2.pdf

 


Et bien, TSMC et Samsung semblent apprecier nos scientifiques, que ca soit CNRS ou CEA-Leti.


Message édité par gliterr le 14-05-2014 à 20:07:52
n°9203175
BIERMAN
§¤§ 19 years of HFR sanity §¤§
Posté le 10-07-2014 à 14:50:26  profilanswer
 
n°9208009
Invite_Sur​prise
Racaille de Shanghaï
Posté le 15-07-2014 à 18:38:44  profilanswer
 

Intel to unveil 14nm processors and 10nm wafers at IDF San Francisco - Digitimes
 

Citation :

Despite delaying its 14nm processor mass production to the fourth quarter of 2014, Intel is still set to showcase its 14nm processors at Intel Developer Forum (IDF) in San Francisco in September as originally scheduled, according to sources from the upstream supply chain. Intel will also unveil its 10nm wafers at the show.


 

Citation :

Because of weaker-than-expected yields, high 22nm processor inventories, and poor PC demand, Intel has postponed 14nm processor production, which is planned to be conducted at its Fab 42 in Arizona, the US, the sources said.


 

Citation :

Intel is now targeting orders for Apple's A9 processor and could become a big threat against the current OEM TSMC because of Intel and Apple's tight relationship, the sources added.

n°9243094
Invite_Sur​prise
Racaille de Shanghaï
Posté le 19-08-2014 à 13:27:40  profilanswer
 
n°9243095
BIERMAN
§¤§ 19 years of HFR sanity §¤§
Posté le 19-08-2014 à 13:31:14  profilanswer
 

J'avais vu cette annonce mais étant faible, quand j'ai vu Guillaume l'auteur, je l'ai zappée [:outlaw6:4]
Et d'ailleurs, je la rezappe :d !!!!!!


Message édité par BIERMAN le 19-08-2014 à 13:31:52

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▬© Base CBR15 ▬© CABASSE ▬© CM AM3+ 100% &- ▬© o/c C2D&Q i7 matuer†
n°9243746
Xixou2
Posté le 19-08-2014 à 21:30:10  profilanswer
 

Invite_Surprise a écrit :

Samsung Now Mass Producing Industry’s Most Advanced DDR4, Using 20 Nanometer-class Process Technology
 
http://tof.canardpc.com/preview2/1 [...] 4abe5f.jpg
 

Citation :

With the introduction of these high-performance, high-density DDR4 modules, Samsung can better support the need for advanced DDR4 in rapidly expanding, large-scale data centers and other enterprise server applications.
 
Early market availability of the 4-gigabit (Gb) DDR4 devices, which use 20 nanometer (nm)-class* process technology, will facilitate demand for 16-gigabyte (GB) and 32GB memory modules. This compares to conventional DRAM of which 8GB modules using a 30nm-class* process technology are still commonplace.


 

Citation :

Editors’ Note: 20 nm-class means a process technology node somewhere between 20 and 30 nanometers, 30 nm-class means a process technology node somewhere between 30 and 40 nanometers, and 50 nm-class means a process technology node somewhere between 50 and 60 nanometers.



 
Commique, ça sera en vente le même jour, de cette année ^^


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