Samsung Plans to Finalize DDR4 Specification in 2011
[01/04/2011 09:55 PM]
by Anton Shilov
 
Samsung Electronics, the largest producer of dynamic random access memory (DRAM), on Tuesday said that it completed development of the industry's first DDR4 memory module last month, using 30nm-class process technology.
 
The new DDR4 DRAM module can achieve data transfer rates of 2133Gb/s at 1.2V, compared to 1.35V and 1.5V DDR3 DRAM at an equivalent 30nm-class process technology, with speeds of up to 1.6Gb/s. When applied to a notebook, it reduces power consumption by 40% compared to a 1.5VDDR3 module.
 
The module makes use of pseudo open drain (POD), a new technology that has been adapted to high-performance graphic DRAM to allow DDR4 DRAM to consume just half the electric current of DDR3 when reading and writing data. By employing new circuit architecture, Samsung's DDR4 will be able to run from 1.60GHz up to 3.20GHz compared to today's typical speeds of 1.6GHz for DDR3 and 800MHz for DDR2.
 
Late last month, Samsung provided 1.2V 2GB DDR4 unbuffered dual in-line memory modules (UDIMM) to a controller maker for testing.
 
"Samsung has been actively supporting the IT industry with our green memory initiative bycoming up with eco-friendly, innovative memory products providing higher performance and power efficiency every year. The new DDR4 DRAM will build even greater confidence in our cutting-edgegreenmemory, particularly when we introduce 4Gb DDR4-based products using next generation process technology for mainstream application," said Dong Soo Jun, president of memory division at Samsung Electronics.
 
Samsung now plans to work closely with a number of server makers to help insure completion of JEDEC standardization of DDR4 technologies in the second half of this year.

IBM et Samsung ont annoncé qu’ils allaient travailler ensemble sur de nouveaux semiconducteurs et les processus de fabrication nécessaires pour graver en 20 nm et moins.
De la nécessité de collaborer
 
Les investissements toujours plus importants, la pression technologique d’Intel et le fait que les marchés tentent encore de suivre la conjecture de Moore obligent les fondeurs à travailler ensemble. Ce partenariat n’est pas surprenant, Samsung appartenant au fab club depuis longtemps. Néanmoins, pour la première fois, les chercheurs coréens rejoindront ceux d’IBM dans les laboratoires new-yorkais de ce dernier.
Une étape importante pour Samsung
 
Les travaux devraient se concentrer sur la structure des transistors, les interconnexions, le packaging et les matériaux permettant de répondre aux défis physiques liés à cette nouvelle finesse de gravure. Ce partenariat pourrait aussi signifier que Samsung va finalement utiliser des couches isolantes de forte permittivité électrique (high-k), à l’instar d’Intel et AMD, ce dernier ayant commencé avec ses premières puces Fusion.
 
Nous sommes aussi en droit de nous demander comment les deux sociétés résoudront leur différend portant sur l’utilisation de la technologie gate-first ou gate-last (voir ici http://www.presence-pc.com/actualite/gate-last-41563/ )

La transition vers le 22 nm devrait coûter 9 milliards de dollars à Intel qui dépendera alors de quatre usines au lieu de trois actuellement.
 
En effet, lorsque le fondeur commercialise une nouvelle finesse de gravure, il a tendance à compter sur trois usines pour assurer la production des nouvelles puces. Ses motifs pour passer à une quatrième sont simples. L’augmentation de la complexité des processus de fabrication à chaque nouvelle étape technologique oblige Intel à mettre ses usines à jour plus rapidement afin de maximiser les profits possibles grâce à la miniaturisation des transistors.
 
Intel espère aussi pénétrer le marché des terminaux mobiles et le 22 nm pourrait être la clé qui lui ouvre de nouvelles portes. Il serait donc nécessaire de disposer de quatre usines modernes au lieu de trois pour assurer la hausse de la demande liée à la diversification de son catalogue. La production des premières puces commercialisables et gravées en 22 nm devrait commercer d’ici la fin de l’année.

 
Logo IntelIntel avait dévoilé son premier microprocesseur gravé à une finesse de gravure de 32 nanomètres en février 2009. La production de masse avait commencé en septembre 2009, et le premier lancement commercial eut lieu en janvier 2010. Si ce déploiement fut particulièrement réussi, on notera cependant qu'il manque encore une déclinaison du 32 nm qui manque à l'appel : celle destinée aux puces à basse consommation.
 
Le retard des Atom « Medfield » qui exploitent ce processus de gravure spécial est préjudiciable à Intel, qui ne peut guère lutter contre ARM sur le segment en pleine expansion des solutions mobiles. La transition vers le 22 nanomètres marquera cependant un changement de taille pour le fondeur, puisque la quasi-totalité de ses gammes de puces passera en très peu de temps à cette nouvelle finesse de gravure ! Si les processeurs « Ivy Bridge » (évolutions des récemment lancés « Sandy Bridge ») seront bien les premiers à être gravés à 22 nm, les Xeon et Atom suivront rapidement.
 
Intel reconnait donc l'évolution de l'industrie, et investit une somme considérable dans ce changement de tactique. Alors qu'habituellement ce sont trois usines qui sont mises à jour à chaque nouvelle finesse, le 22 nm sera déployé sur quatre usines dès le départ ! Coût total pour le géant de Santa Clara : 9 milliards de dollars ! 2,7 milliards de dollars seront également investis dans l'usine israélienne du géant de Santa Clara, qui pourrait produire ses premières puces à 22 nm dès le mois de décembre. Intel doit produire en masse ses premiers CPU à 22 nm dès le quatrième trimestre 2011, même si le lancement officiel des premiers Ivy Bridge n'aura probablement pas lieu avant 2012.

With the transition to 22nm process technology that will start later this year Intel Corp. will also move to a new manufacturing model that will rely on four leading-edge fabs instead of three. The plan will cost Intel $9 billion this year, but Intel claims that with 22nm manufacturing process it will be able to enter a number of new markets.
 
"In support of expected strong unit growth in our core businesses and the movement of graphics transistors to our leading edge process technology, we are forecasting an increase in capital spending to $9 billion as we build and equip an incremental high volume manufacturing factory at 22nm," said Stacy Smith, chief financial officer of Intel, during the most recent quarterly conference call with financial analysts.
 
At present Intel expects to rapidly transit its PC and server processors as well as various chips for low-power and mobile applications to 22nm fabrication process. Since previously the company transited its Atom and low-cost products to newer nodes around a year after premium chips, but with the 22nm the latest fabrication process will be applied for the whole product stack.
 
"As we approach our 22nm transition, we are increasing our investments in manufacturing to capture what we believe is a significant opportunity for growth. [...] The market opportunities for our 22nm products are outstanding. As a result, we are growing from the model of three high volume leading-edge manufacturing fabs to four. Our 22nm process will be the foundation for growing PC and server segments, as well as a broad family of Atom-based SoCs, serving smartphones, tablets, smart TVs, and other embedded devices," said Paul Otellini, chief executive officer of Intel.
 
In fact, mobile devices seem to have a very high priority for the world's largest maker of microprocessors.
 
"We are building some on 32nm now and then the initial products on 22nm will be the mainstream microprocessors, because we want to use every early wafer we can for those products, but we will move as rapidly to 22nm as possible for the non-PC part of the product line," explained the head of Intel.
 
While it is very likely that Intel will start making commercial chips using 22nm fabrication process already in Q4 2011, the company itself does not want to make any official promises concerning mass production or revenue shipments just now.
 
"We have finished development of the process. We are in yield learning deployment right now, running test ships in there, ramping the yields up on the technology. We have completed the design of our first microprocessor and have working microprocessors on that technology. At this point in time our plan is to ramp production wafers of that technology in the second half of this year with products launched at some point to follow," said Mr. Otellini.
 
Among the most anticipated 22nm products from Intel are code-named Ivy Bridge microprocessors for desktops, laptops and servers as well as Knights Corner accelerator based on MIC [many Intel core] architecture. Intel has already confirmed that it does have working samples of 22nm chips.

THE FINAL KEYNOTE of the Common Platform conference was given by IBM's Garry Patton, and he talked collaboration and tech. The list of new things thrown out was pretty dizzying, but what do you expect from someone who is in charge of semiconductor R&D?
 
The most interesting part of the whole discussion was how the collaboration chain was expanding because of increased technical complexity. In the past, the fabrication processes used to be worked on, and late in the game, the tool vendors were brought in to write the software and simulations that were needed for design.
 
From that point, the tools were given to the end users, and they designed their chips with them. It was all bundled up in the end and shipped off to the fab of choice. That whole process doesn't really work anymore.
 
For the last node or three, tool vendors have been playing an increasingly important role in making the whole process work. They are being brought in sooner and sooner in the development process, and the tools are somewhat co-developed with the chemistry. The two are inseparable now, but the whole thing was still given to customers as a package when done.
 
Unfortunately, the whole chain is now so complex, and the designs that use them are similarly complex, that foundries are needing design partner input in the tools. This may sound like a good idea, but there is a lot to manage, especially if you have to bring in everyone that can potentially make a chip with a process before the process is fully baked. Herding cats is comparatively easy.
 
No matter who you bring in, and how you bring them in, the whole idea of collaborative R&D and collaborative design enablement is here to stay. Things are only going to get worse from here on out, and the only way to mitigate some of it is to bring all the players together early. Once again, group hug time.
 
From there, things went back to tech, and the group hugging was finished for the keynote sessions. It started out on a down note, that gate scaling was effectively dead. This is widely known, not a shock to anyone following the industry, but it is still a fairly hard roadblock. While you won't get much, if any, smaller from here on out, gate innovation is far from dead.
 
With that stake planted in the sand, there was lots of new stuff to talk about, starting with a roadmap for the upcoming nodes. The Common Platform guys are still saying that they are on a 2 year shrink cycle, with 20nm coming in 2012, 14nm in 2014, and 11nm in 2016. At least to the 14nm node, maybe 11nm, the roadmaps seem fairly firm.
 
According to slides shown by Mr Patton, the big step for lithography on 32/28nm is 'second generation immersion'. 20nm brings Source Mask Optimization(SMO) and 3rd gen immersion to the fray, upping to 4th gen at 14nm. In addition to SMO, 14nm also uses double patterning.
 
EUV is a hot topic among fab people now, and the Common Platform partners seem to think that it is possible for some 14nm layers, but not definite. I think it is more a question of tools availability, materials availability, and cost of running them more than anything else. Even 11nm is listed as "EUV (or DPL)" (double patterning).
 
What is Source Mask Optimization (SMO)? That is probably the most interesting bit. SMO is a fancy way of saying changing the (light) source to work around limits of the mask. Masks currently are using diffractive optical elements (DOE) to make patterns smaller than the wavelengths used to draw them, but that can't work forever.
 
The key to SMO is a pixelated light source, something that gets interesting when you are talking about EUV lasers. If you can change the source on the fly, you can add a whole bag of tricks to mask creation. The closest SemiAccurate got to an explanation was a projection TV micromirror array to turn pixels on and off. Currently, ASML and Zeiss are working on one, but not at the EUV level. This should be very fun to watch as it develops.
 
Moving on to the transistors themselves, the roadmap went out a bit farther. 22nm was listed as using PDSOI and bulk silicon, basically the same choices as we have now. At 14nm, Common Platform will use FinFETs, and 11nm may add ETSOI (Extremely Thin SOI) to the mix. This is likely still in a bit of flux though, we are talking about 2018 for a possible introduction.
 
On the 8nm, 5nm and 3nm nodes, things get a little more theoretical. OK, a lot more theoretical. 8 and 5nm are listed as using silicon nanowires plus a fully depleted SOI substrate, and 3nm moves on to some kind of carbon, be it nanotubes or otherwise. Given the timelines involved, anything could be a contender below 11nm.
 
Getting back to the optimistic side, Mr Patton did state that they have working FinFETs in the labs now at 14nm, and they have working carbon ring oscillators at sub-14nm geometries as well. As was said earlier, making one is easy, a few billion or trillion is a completely different problem. That brings us to the last topic of the day, gate first vs gate last. The Common Platform vendors are going to gate last at 20nm, that much is certain.
 
Why are they doing it? Officially, the pros of gate last outweighed the cons, and the partners had the requisite group hug and decided that it was the right thing to do together. Inside sources tell SemiAccurate that there was no hugging involved, more knives and blood, but the end result is gate last. If you look at some of the yield headaches Llano was having, you might just come to the conclusion that some partners did not want to repeat that at 20nm.
 
Officially, there were four factors involved with the decision, density, scaling from the previous node, process complexity, and power/performance. Gate first is much denser, a claimed 10-20% more transistors per unit area. That of course is balanced out by lower yield of the gate first process, but depending on a lot of variables, the end result, cost, could go either way.
 
Scaling from the previous node is clearly on the gate first side. Gate last needs radically different design rules, so first is much simpler to work with. The flip side of that is once you go to gate last design rules, and if you stay there, the next node has an easier path to gate last too. From 32/28nm though, gate first at 20nm is the way to go if this is the only consideration.
 
Process complexity is a clear win for gate first too. You put the gate in and you have to protect it for some of the later steps, but that is not the end of the world. Gate last makes you put in a dummy gate, do the rest of the chip, etch the dummy out, and then put in a new gate. This isn't exactly trivial, but as Intel has shown, it is quite doable. Gate first is much simpler, but Intel and TSMC seem to think the increased yield from gate last is worth the pain.
 
The last consideration is power/performance. IBM said at a later Q&A session that gate first has a 6% power/performance advantage over gate last. Gate first also needs less strain engineering, but gate last seems to benefit more from it. This ends up as a win for gate last.
 
In the end, it is impossible to pick a winner without hard data. On the 32/28nm node, the Common Platform companies went with gate first, Intel and TSMC are using gate last. Neither side is doing it on a whim, so there are obviously benefits to both methods. On 22/20nm, everyone is going with gate last, so the question is unequivocally answered. Group hug time again?
 
Where does that leave us? Group hugs are not a bad analogy as it turns out. Everyone involved in the chip making process, from the tool vendors and the materials vendors to the chip designer needs to get involved earlier. Each new node brings more and more complexity to the game, so everyone will eventually be brought in to the process, pun intended.
 
The Common Platform group has laid out a roadmap to 14nm that is pretty solid, and shown tidbits of things after that. Will they all work? What will end up in use, and what will end up panning out? Who knows, but it looks like scaling will be with us for some time to come.

IBM est à la pointe de la recherche en électronique et a fait l'éloge à plusieurs reprises des transistors en graphène. Big Blue tempère aujourd'hui son propre enthousiasme en estimant que le graphène ne pourra pas remplacer totalement le silicium dans nos puces.
 
Le problème, tel que souligné par Yu-Ming Lin employé de IBM Research - Nanometer Scale Science and Technology, est que les transistors en graphène ont un faible ratio On/Off. Le ratio On/Off est le rapport entre le courant traversant le transistor lorsqu'il est en position On et lorsqu'il est en position Off. Si ce rapport est trop faible, il devient difficile de savoir si le transistor est en état On ou Off.
 
Les transistors en graphène conservent néanmoins de très grands avantages : ils peuvent être théoriquement beaucoup mieux miniaturisés, et atteignent des fréquences de fonctionnement bien supérieures à taille identique que leurs homologues en silicium. Yu-Ming Lin estime donc qu'ils pourront être complémentaires du silicium à l'avenir, dans des circuits ne nécessitant pas un ratio on/off très élevé.

Pour faire simple, un feuillet bidimensionnel de molybdénite de 0,65 nanomètre est un excellent semi-conducteur, alors que dans les mêmes conditions, le silicium se limite à 2 nanomètres.

Rambus ne fait pas que des procès à ses concurrents pour violation de brevets, la société investit aussi beaucoup d'efforts en R&D. Dernièrement, elle a annoncée une nouvelle technologie de mémoire vive promettant des débits de 20 Gbps, là où la DDR3 culmine à 2,4 Gbps et la GDDR5 à 7 Gbps.
 
Cette nouvelle interface mémoire serait en outre rétrocompatible avec la DDR3 et la GDDR5 ce qui garantit une évolution en douceur pour tous les fabricants qui la choisiraient. Rambus met également en avant une grande efficacité énergétique puisque sa mémoire ne consomme que 6 mW par Gbps avec des composants gravés en 40 nm.

Rambus ne fait pas que des procès à ses concurrents pour violation de brevets, la société investit aussi beaucoup d'efforts en R&D.

Cette nouvelle interface mémoire serait en outre rétrocompatible avec la DDR3 et la GDDR5 ce qui garantit une évolution en douceur pour tous les fabricants qui la choisiraient. [...]

Intel is co-funding a research and production centre at the University of Washington, which it hopes will lead to breakthroughs in the field of silicon photonics.
 
The deal, which was reported this week in Chip Design Magazine, will see Intel dip into its recent monster profits to fund the foundation of the Optoelectronics Systems Integration in Silicon (OpSIS) Centre at the University, designed as the silicon photonics equivalent of the Metal Oxide Semiconductor Implementation Service Centre at the University of Southern California.
 
Rather than relying on electrical connections between components, photonics instead transfers data over optical connections. Intel has already dabbled with high-speed optical data connections with its Light Peak technology, but it's hoped that photonics could enable optical connections inside mass-produced chips as well.
 
Michael Hochberg, assistant professor of electrical engineering at the University, stated that the University would 'like the photonics industry, 10 years from now, to function in a way that’s very similar to the electronics industry today. People building optoelectronic systems will send designs out to an inexpensive, reliable third party for manufacturing, so they can focus on being creative about the design.'
 
Intel's chief technology officer Justin Rattner was also confident about the success of the project, claiming 'OpSIS will enhance the education of US engineering students, giving them the opportunity to learn the new optical design paradigm. The ability to produce such low-cost silicon chips that manipulate photons, instead of electrons, will lead to new inventions and new industries beyond just data communications, including low-cost sensors, new biomedical devices and ultra-fast signal processors.'
 
Intel is far from the only company investing in optical computing and silicon photonics, though. Back in 2007, IBM announced the creation of a micro-miniaturised Mach-Zenhder electro-optic modulator, which it hoped would lead to a revolution in optical computing technology.
 
Once up to speed, the OpSIS Centre looks to offer three production runs per year, each capable of making chips for 30-40 users. Meanwhile, the physical production will be left in the hands of BAE Systems.
 
Are you pleased to see Intel looking into the potential of silicon photonics, or should the company be spending its money elsewhere? Share your thoughts over in the forums.

US researchers have successfully assembled a tiny processor from nanometre-scale components to perform basic arithmetic and logical functions.
 
Harvard University's Charles M. Lieber and his team built 960μm2 (square micrometre) 'logic tiles' that could perform adder, subtractor, multiplexer, demultiplexer and clocked D-latch functions.
 
The tiles each contained 496 programmable transistors built from ten-nanometre-thick germanium wires, and were touted as a "world first" in complexity and function.
 
In a research paper published in Nature today, the researchers described designing, constructing and using the programmable tiles.
 
"For the past 10 to 15 years, researchers working with nanowires, carbon nanotubes, and other nanostructures have struggled to build all but the most basic circuits, in large part due to variations in properties of individual nanostructures," stated Lieber, who collaborated with the MITRE Corporation on the project.
 
"This work represents a quantum jump forward in the complexity and function of circuits built from the bottom up.
 
"[It] thus demonstrates that this bottom-up paradigm, which is distinct from the way commercial circuits are built today, can yield nanoprocessors and other integrated systems of the future."
 
Since each tile had a maximal voltage gain of ten and could match input-outage voltage levels, they could be arranged into linear or tree-like interconnected arrays, the researchers wrote.
 
In the near term, the technology could yield simpler, low-power, application-specific 'nanocontrollers' for use in tiny embedded systems and biomedical devices, they suggested.
 
Lieber acknowledged in Nature News that the chip would struggle to compete with conventional electronics, which crammed far more transistors onto a single chip.
 
Each of Harvard's nanotransistors occupied 1.9μm2 - more than twenty times the 0.09μm2 area required by logic gates in current 32nm CMOS chips, the researchers wrote (pdf).
 
The Intel Sandy Bridge, which launched in Australia last month, fit each of its 995 million transistors into a 0.217μm2 area, with a total area of 216mm2 (square millimetres).
 
Lieber and his team said their chip could be further improved to be up to 100 times more efficient than current electronics, and require only 0.0017μm2 per transistor.

(Nanowerk News) A fundamental component of a field-effect transistor (FET) is the gate dielectric, which determines the number of charge carriers—electrons or electron vacancies—that can be injected into the active channel of the device. Graphene has recently become the focus of attention as a viable, high-performance replacement for silicon in FETs, and in recent studies on graphene-based FETs, scientists have investigated the use of thin films of a ferroelectric material for the gate dielectric. Such films offer several interesting advantages for use in graphene-based FETs: their strong electrical polarization makes it possible to introduce a much higher density of carriers than can be achieved using standard dielectrics, and they have remnant electric polarization—a property that could allow graphene–ferroelectric FETs to be used for nonvolatile memory by storing a certain level of carrier density in the absence of an electrical field.
 
Two collaborating teams from the A*STAR Institute of Materials Research and Engineering and the National University of Singapore, led by Kui Yao and Barbaros Özylmaz, respectively, previously demonstrated a basic graphene–ferroelectric memory device in which the polarization in the ferroelectric film was controlled by the electrical bias applied to the gate terminal. In that structure, a thin ferroelectric film was deposited on top of a graphene layer, where it injects charge carriers and thus modulates the resistance of the graphene. Unfortunately, however, the two distinct resistance states that could be read as an information bit could only be realized by polarizing and depolarizing the ferroelectric film, which presented problems due to the instability of the depolarization state.
 
Now, the two teams have collaborated to fabricate an improved device ("Graphene Field-Effect Transistors with Ferroelectric Gating" ) that includes an additional silicon dioxide (SiO2) dielectric gate below the graphene layer (see image). The SiO2 gate, a long-standing component in traditional FETs, effectively provides a reference point from which to measure the effect of ferroelectric gating. By monitoring the resistance of the device as a function of the voltages applied to the top and bottom gates, the researchers developed a quantitative understanding of the performance and switching behavior of graphene–ferroelectric FETs. For use as a nonvolatile memory device, the SiO2 dielectric gate also simplifies bit writing by providing an additional background source of charge carriers, allowing the ferroelectric polarization to be switched between two stable states corresponding to two opposite polarization orientations.
The new device developed by the research team achieved impressive practical results, capable of symmetrical bit writing with a resistance ratio between the two resistance states of over 500% and reproducible nonvolatile switching over 100,000 cycles.

Scientists claim that a new method for creating materials in sheets that are just one-atom-thick could lead to breakthroughs in data and energy storage technologies, meaning bigger storage devices and longer-lasting batteries.
 
According to coverage of the discovery over on Reuters, quoting a report published in journal Science, the technique makes it significantly easier to create one-atom-thick sheets of different materials, including graphene sheets made from carbon.
 
Work has been done in the past on creating graphene, but the material - which is just one-atom-thick and around a hundred times stronger than steel - remains expensive and difficult to produce; something the researchers believe they may have solved.
 
The new method is claimed to be low-cost, while also resulting in extremely high yields of usable materials, but isn't just limited to producing sheets from carbon. Instead, the researchers claim they can use the technology to create single-atom sheets from a variety of elements, drastically changing their electrical and thermoelectric properties and potentially unlocking useful new materials.
 
While graphene in its current state may not completely replace silicon the semiconductor industry, according to IBM, this latest work could help find the materials and technologies that mean faster, longer-lasting electronic circuits in the future.
 
Are you pleased to see researchers coming up with potential new materials in this way, or will you only get excited when the technology gets commercialised? Share your thoughts over in the forums.

Physicists from the University of Bonn have developed a completely new source of light, a so-called Bose-Einstein condensate consisting of photons. Until recently, expert had thought this impossible. This method may potentially be suitable for designing novel light sources resembling lasers that work in the x-ray range. Among other applications, they might allow building more powerful computer chips. The scientists are reporting on their discovery in the upcoming issue of the journal Nature.
 
By cooling Rubidium atoms deeply and concentrating a sufficient number of them in a compact space, they suddenly become indistinguishable. They behave like a single huge "super particle." Physicists call this a Bose-Einstein condensate.
 
For "light particles," or photons, this should also work. Unfortunately, this idea faces a fundamental problem. When photons are "cooled down," they disappear. Until a few months ago, it seemed impossible to cool light while concentrating it at the same time. The Bonn physicists Jan Klärs, Julian Schmitt, Dr. Frank Vewinger, and Professor Dr. Martin Weitz have, however, succeeded in doing this – a minor sensation.
 
How warm is light?
 
When the tungsten filament of a light bulb is heated, it starts glowing – first red, then yellow, and finally bluish. Thus, each color of the light can be assigned a "formation temperature." Blue light is warmer than red light, but tungsten glows differently than iron, for example. This is why physicists calibrate color temperature based on a theoretical model object, a so-called black body. If this body were heated to a temperature of 5,500 centigrade, it would have about the same color as sunlight at noon. In other words: noon light has a temperature of 5,500 degrees Celsius or not quite 5,800 Kelvin (the Kelvin scale does not know any negative values; instead, it starts at absolute zero or -273 centigrade; consequently, Kelvin values are always 273 degrees higher than the corresponding Celsius values).
     
   

IMAGE: The creators of the "super-photon " are Julian Schmitt (left), Jan Klaers, Dr. Frank Vewinger and professor Dr. Martin Weitz (right).  
 
When a black body is cooled down, it will at some point radiate no longer in the visible range; instead, it will only give off invisible infrared photons. At the same time, its radiation intensity will decrease. The number of photons becomes smaller as the temperature falls. This is what makes it so difficult to get the quantity of cool photons that is required for Bose-Einstein condensation to occur.
 
And yet, the Bonn researchers succeeded by using two highly reflective mirrors between which they kept bouncing a light beam back and forth. Between the reflective surfaces there were dissolved pigment molecules with which the photons collided periodically. In these collisions, the molecules 'swallowed' the photons and then 'spit' them out again. "During this process, the photons assumed the temperature of the fluid," explained Professor Weitz. "They cooled each other off to room temperature this way, and they did it without getting lost in the process."
 
A condensate made of light
 
The Bonn physicists then increased the quantity of photons between the mirrors by exciting the pigment solution using a laser. This allowed them to concentrate the cooled-off light particles so strongly that they condensed into a "super-photon."
 
This photonic Bose-Einstein condensate is a completely new source of light that has characteristics resembling lasers. But compared to lasers, they have a decisive advantage, "We are currently not capable of producing lasers that generate very short-wave light – i.e. in the UV or X-ray range," explained Jan Klärs. "With a photonic Bose-Einstein condensate this should, however, be possible."
 
This prospect should primarily please chip designers. They use laser light for etching logic circuits into their semiconductor materials. How fine these structures can be is limited by the wavelength of the light, among other factors. Long-wavelength lasers are less well suited to precision work than short-wavelength ones – it is as if you tried to sign a letter with a paintbrush.
 
X-ray radiation has a much shorter wavelength than visible light. In principle, X-ray lasers should thus allow applying much more complex circuits on the same silicon surface. This would allow creating a new generation of high-performance chips - and consequently, more powerful computers for end users. The process could also be useful in other applications such as spectroscopy or photovoltaics.
 
###
 
Contact:
Prof. Dr. Martin Weitz
Institut für Angewandte Physik der Universität Bonn
Ph: +49 228/73-4837 or -4836
Email: Martin.Weitz@uni-bonn.de
 
Jan Klärs
Institut für Angewandte Physik der Universität Bonn
Ph: +49 228/73-3453
Email: klaers@iap.uni-bonn.de  

Intel Corp. on Friday announced plans to invest more than $5 billion to build a new chip manufacturing facility at its site in Chandler, Arizona. Although the company is looking forward 450mm chip fabs, the new factory will process 300mm wafers at least initially.
 
The new Arizona factory, designated Fab 42, will be the most advanced, high-volume semiconductor manufacturing facility in the world, according to Intel. Construction of the new fab is expected to begin in the middle of this year and is expected to be completed in 2013. The new factory will make chips using 14nm manufacturing process on 300mm wafers.
 
“The investment positions our manufacturing network for future growth. This fab will begin operations on a process that will allow us to create transistors with a minimum feature size of 14nm. For Intel, manufacturing serves as the underpinning for our business and allows us to provide customers and consumers with leading-edge products in high volume. The unmatched scope and scale of our investments in manufacturing help Intel maintain industry leadership and drives innovation, ,” said Brian Krzanich, senior vice president and general manager of manufacturing and supply chain at Intel.
 
The project will create thousands of construction and permanent manufacturing jobs at Intel’s Arizona site.
 
While more than three-fourths of Intel’s sales come from outside of the United States, Intel manufactures three-fourths of its microprocessors in the United States. The addition of this new fab will increase the company’s American manufacturing capability significantly.
 
“The products based on these leading-edge chips will give consumers unprecedented levels of performance and power efficiency across a range of computing devices from high-end servers to ultra-sleek portable devices,” added Mr. Krzanich.

Anis Daami, un chercheur français travaillant au CEA à Grenoble a présenté une méthode permettant d’imprimer des transistors sur du plastique.
 

 
Ce procédé permet en plus de graver des transistors de type p ou n, contrairement au processeur et à la mémoire DRAM dont nous vous parlons dans notre actualité Recherche : le processeur en plastique existe qui n'emploient que des transistors de type p
 
M. Daami a montré une série de puces sur une feuille de plastique de 380 x 320 mm gravés par ablation laser. Très grossièrement, on utilise un laser pulsé pour retirer de la matière et graver les motifs désirés. Les puces en démonstration avaient des canaux de 20 microns de large, mais le scientifique affirme qu’il est possible d’augmenter la finesse.
 
Les puces, d’une architecture relativement simple, étaient fonctionnelles à température ambiante sous des conditions normales d’utilisation, ce qui représente une première mondiale. Jusqu’à présent, ces transistors ne fonctionnaient que sous un environnement très spécial en laboratoire.

Des scientifiques de l’Université du Michigan ont présenté ce qu’ils appellent le processeur tout-en-un à l’échelle du millimètre.
 
Le tout-en-un vient du fait qu’il dispose d’un microprocesseur, d’un capteur, d’une mémoire, une batterie, d’un panneau solaire permettant de l’alimenter en électricité et d’un module radio pour recevoir et transmettre des données. C’est un processeur qui en principe se suffit à lui même. Il est destiné à servir de capteur et être placé dans les yeux de patients victimes de glaucome afin de mesurer la pression intraoculaire et surveiller la progression de la maladie.
 
Les chercheurs envisagent qu’à terme, la médecine pourra insérer des dizaines, voire des centaines de ces petits capteurs dans le corps humain pour surveiller divers de ses aspects. Demandant moins d’un millimètre cube, il consomme en moyenne 5,3 nanoWatts et se réveille toutes les 15 minutes pour prendre ses mesures et transmettre ses résultats. Il faut une heure et demie à la lumière du soleil ou dix heures à la lumière artificielle pour recharger ses batteries.