bjr,
je voudrai changer le timing de ma ram manuellement !
carte mere ms platinum p35 amibios 1.9
ram 2X 1024 ballistix 1066
ma carte mere a mit par defaut des timings qui ne correspondent pas du tout a ceux du constructeur
ceux indiques par crucial sont 5.0 .5.5.15
j ai bien trouver dans le bios de la carte le cell menu ou rentrer les parametres
sauf que dans les derniers parametres, je ne sais pas quoi mettre 
voila un copier coller de la doc du bios pour changer les parametres!
merci .
Configuration DRAM Timing by SPD
Setting to [Enabled] enables DRAM CAS# Latency automatically to be determined
by BIOS based on the configurations on the SPD (Serial Presence Detect) EEPROM
on the DRAM module.
DRAM CAS# Latency
When the Configuration DRAM Timing by SPD sets to [Disabled], the field is
adjustable.This controls the CAS latency, which determines the timing delay (in
clock cycles) before SDRAM starts a read command after receiving it.
DRAM RAS# to CAS# Delay
When the Configuration DRAM Timing by SPD sets to [Disabled], the field is
adjustable. When DRAM is refreshed, both rows and columns are addressed
separately. This setup item allows you to determine the timing of the transition
from RAS (row address strobe) to CAS (column address strobe). The less the
clock cycles, the faster the DRAM performance.
DRAM RAS# Precharge
When the Configuration DRAM Timing by SPD sets to [Disabled], this field is
adjustable. This setting controls the number of cycles for Row Address Strobe
(RAS) to be allowed to precharge. If insufficient time is allowed for the RAS to
accumulate its charge before DRAM refresh, refresh may be incomplete and
DRAM may fail to retain data. This item applies only when synchronous DRAM is
installed in the system.
DRAM TRFC
When the Configuration DRAM Timing by SPD sets to [Disabled], the field is
adjustable. This setting determines the time RFC takes to read from and write to
a memory cell.
DRAM TWR
When the Configuration DRAM Timing by SPD sets to [Disabled], the field is
adjustable. Minimum time interval between end of write data burst and the start
of a precharge command. Allows sense amplifiers to restore data to cells.
DRAM TWTR
When the Configuration DRAM Timing by SPD sets to [Disabled], the field is
adjustable. Minimum time interval between the end of write data burst and the
3-23
BIOS Setup
start of a column-read command. It allows I/O gating to overdrive sense amplifiers
before read command starts.
DRAM TRRD
When the Configuration DRAM Timing by SPD sets to [Disabled], the field is
adjustable. Specifies the active-to-active delay of different banks. Time interval
between a read and a precharge command.
DRAM TRTP
When the Configuration DRAM Timing by SPD sets to [Disabled], thestart of a column-read command. It allows I/O gating to overdrive sense amplifiers
before read command starts.
DRAM TRRD
When the Configuration DRAM Timing by SPD sets to [Disabled], the field is
adjustable. Specifies the active-to-active delay of different banks. Time interval
between a read and a precharge command.
DRAM TRTP
When the Configuration DRAM Timing by SPD sets to [Disabled], the field is
adjustable. Time interval between a read and a precharge command.
merci. 
