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je suis d'accord, il y en a plein le cu de corsaire
SAMSUNG
K4H560838E
8M x 8Bit x 4 Banks Double Data Rate SDRAM
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General Description
The K4H560838E is 268,435,456 bits of double data rate synchronous DRAM organized as 4x 16,777,216 / 4x 8,388,608 words by 4/ 8/ bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 333Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.
Note] Orange text is only about DDR 400
Green text is only about DDR 200/266/333
200MHz Clock, 400Mbps data rate.
166MHz Clock, 333Mbps data rate.
VDD= +2.6V ± 0.10V, VDDQ= +2.6V ± 0.10V
VDD= +2.5V ± 0.20V, VDDQ= +2.5V ± 0.20V
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Bidirectional data strobe[DQ] (x4,x8)
Four banks operation
Differential clock inputs(CK and /CK)
DLL aligns DQ and DQS transition with CK transition
MRS cycle with address key programs
- Read latency 3 (clock) for DDR 400
- Read latency 2.5 (clock) for DDR 333
- Burst length (2, 4, 8)
- Burst type (sequential & interleave)
All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
Data I/O transactions on both edges of data strobe
Edge aligned data output, center aligned data input
DM for write masking only (x8)
DM for write masking only (x4, x8)
Auto & Self refresh
7.8us refresh interval(8K/64ms refresh)
Maximum burst refresh cycle : 8
Message édité par F18 le 28-01-2005 à 18:30:37
