Hi evryone !
 
I have another problem, i get others errors : Line 71: Expression has 32 elements ; expected 16
                                                             Line 47: Expression has 9 elements ; expected 16
the tow lines :
 
Line 47 : wr <= curr_depth_bufbuf;
Line 71 : shift_p <= 2*shift_p;
 
The declarations of generic and ports are the following with the signals also :
 
generic (
MAX_DEPTH : integer := 9; -- max tree depth
HASH_LENGTH : integer := 2; -- hash length in words
BLOCK_LENGTH : integer := 32; -- block length in words
MEM_WIDTH : integer := 16); -- word width
port (
clk : in std_logic;
rstb : in std_logic; -- active low async reset
start : in std_logic; -- start bit
path_depth : in std_logic_vector(MAX_DEPTH-1 downto 0); -- one hot
w_beta : in std_logic_vector(MAX_DEPTH-1 downto 0); -- selected node;
ptr : out std_logic_vector(MEM_WIDTH-1 downto 0); -- pointer value
wr : out std_logic_vector(MEM_WIDTH-1 downto 0); -- enable ptr writre
status : out std_logic); -- finish bit
 
 
signal curr_depth, curr_depth_buf, curr_depth_bufbuf : std_logic_vector(MAX_DEPTH-1 downto 0);
signal leftright, leftright_buf, status_tmp, leaf : std_logic; -- 1 is goto branch 1
signal shift_w, shift_p, w_addr, p_addr : unsigned(MEM_WIDTH-1 downto 0);
constant root_addr : integer := 2**MAX_DEPTH;
 

Line 47: curr_depth_bufbuf is declared as a 9 bits vector and you are trying to store it in wr which is 16 bits

Line 71: shift_p is declared as a 16 bits vector, thus 2* shift_p fits on 17 bits. I guess something is wrong with the error you get, but code is indeed incorrect.

You did not provide enough data on what you are trying to acheive for me to suggest a correction.