“My day job is working on [research for a process to make] 7 nm [chips and] I believe there is a way without EUV,” said Intel fellow Mark Bohr, responding to a question after a talk on Intel’s new 14 nm process.

“I am very interested in EUV [because it] could really help scaling and perhaps process simplification, reducing three or four masks to one in some cases,” Bohr said. “Unfortunately, it’s not ready yet -- the throughput and reliability are not there.”

Intel already announced it has started making in volume chips using a 14 nm process at a lower cost per transistor than its prior 22 nm generation. It also said it is in development of a 10 nm process that it believes will deliver lower cost per transistor.

In his most detailed talk to date, Sunit Rikhi, general manager of Intel’s custom foundry business, described the details of an end-to-end service that’s now more open than ever but still evolving.
Customers are currently using their own designs, supplemented with some IP blocks from Synopsys and Cadence. In the future, Intel will offer some IP, starting with an Atom core still in development.

Most significantly, Intel is far along in testing a lower-cost alternative to 2.5D chip stacks it calls the Embedded Multi-Die Interconnect Bridge.
 
Unlike the 2.5D process, EMIB does not lay dies side-by-side on large silicon interposers, connecting them with through silicon vias (TSVs). Instead it uses a more conventional kind of flip chip process with metal bump interconnects inside a package.

TSMC today announced that its collaboration with HiSilicon Technologies Co, Ltd. has successfully produced the foundry segment's first fully functional ARM-based networking processor withFinFET technology. This milestone is a strong testimonial to deep collaboration between the two companies and TSMC's commitment to providing industry-leading technology to meet the increasing customer demand for the next generation of high-performance, energy-efficient devices.
 
TSMC's 16FinFET process promises impressive speed and power improvements as well as leakage reduction. All of these advantages overcome challenges that have become critical barriers to further scaling of advanced SoC technology. It has twice the gate density of TSMC's 28HPM process, and operates more than 40% faster at the same total power, or reduces total power over 60% at the same speed.

TSMC's 16FinFET has entered risk production with excellent yields after completing all reliability qualifications in November 2013. This paves the way for TSMC and customers to engage in more future product tape-outs, pilot activities and early sampling.
 
"We are delighted to see TSMC's FinFET technology and CoWoSsolution successfully bringing our innovative designs to working silicon," said HiSilicon President Teresa He."This industry's first 32-core ARM Cortex-A57 processor we developed for next-generation wireless communications and routers is based on the ARMv8 architecture with processing speeds of up to 2.6GHz.

Park Yu-ak, an analyst at Meritz Securities, said, "Global AP makers are likely to focus on lowering the cost of production this year in order to offset a decline in AP prices." He added, "Samsung's system semiconductor business is going to mass produce and supply chips to Apple, Qualcomm, and Nvidia starting in the second quarter of this year. As a result, the Korean tech giant is projected to exhibit stellar performance."

Today was TSMC's 2015 North American Technology Symposium. They talked about a lot of things but perhaps the most important was that they gave a lot of details of new processes, new fabs, and volume ramps.

16FF+
This is the second generation of TSMC's 16FF process. Volume production will be mid-2015, which is just one-year after 20nm volume production started. TSMC already has over a dozen tape-outs and expects to have over 50 by the end of 2015. The process has 10% better performance than competitors and 50% less power than 20nm.

10FF
TSMC said this is ahead of schedule. They have already built and yielded a 256Mb SRAM. The density of 10nm will be 2.1x that of 16nm node partially due to a new local interconnect layer and partially because they are using self-aligned spacer (aka SADP or SIT) on the metal. SRAM cell shrinks by 0.46 to 0.49. Risk production will be 4Q2015. Test chip based on ARM Cortex A-57 taped out 2 weeks ago. There is a 19% speed gain or 38% power reduction based on this test chip.

16FFC
This is, I believe, a process newly announced today. It is a more compact version of 16FF+ aimed at the consumer marketplace. Same design rules. Simpler process, tighter process corners. Power is reduced by over 50% and the pricing is cost-competitive for mainstream markets (which I take as meaning it is cheaper than 28nm for the same design). Voltage is 0.55V. Version 1.0 collateral will be available 1Q2016 with customer tape-outs in 2H2016.

EE Times: When will the first chip (based on Globalfoundries’ 22nm FD-SOI) become commercially available?
 
Jha: We are expecting the production tape-out to be in the second half of 2016.

EE Times: For 14nm node, Globalfoundries depended on the technology licensed from Samsung. What’s your plan for 10nm and 7nm? Will you develop your own technologies?
 
Jha: We’re developing our own technologies for the next nodes. The whole point of the IBM Microelectronics business acquisition is to leverage IBM’s technologists and technology to accelerate our own development of leading-edge process technologies.

EE Times: FinFET promoters already have a roadmap for 10nm and 7nm. What’s the FD-SOI roadmap beyond 22nm?
 
Jha: We have an FD-SOI roadmap that also scales. We’re currently exploring with our partners if we should use a different tool set for the next node. If it turns out to be different, we’ll do the next-node FD-SOI production in Malta, NY, while Dresden remains focused on 22nm FDX.

The road map suggests TSMC could leapfrog Intel to producing 10nm chips, although naming conventions for nodes these days hide the underlying details of the processes. What's more clear is TSMC has gotten off to a slow start with its 16nm FinFET process with close partners such as Xilinx saying they have taped out but not yet shipped their first chip in the process. Xilinx also plans to skip TSMC’s 10mn process in favor of its 7nm node, a significant choice given Xilinx typically acts as a logic driver for new TSMC nodes.

TSMC has made a working SRAM at 7nm, Sun reported. The node should deliver 40-45% less area and either 10-15% higher speeds or 25-30% lower power than the 10nm node, he said.
 
The foundry expects to start “risk” production for 7nm in the first quarter of 2017. It is developing the process for existing immersion steppers, Sun told EE Times. Nevertheless, Sun reported progress with EUV systems now running at 90W and expected to have throughput as high as 125 wafers/hour later this year.

"TSMC could face tough competition as soon as 2018 or 2019 as Intel is likely to gain orders from Apple by then," Samuel Wang, a veteran semiconductor analyst at research company Gartner, told the Nikkei Asian Review. "Intel has begun to engage with Apple and it aims to grab one or two top-tier customers from TSMC."

A senior Taiwanese chip industry executive shared Wang's views. "Intel is definitely the most formidable challenger for TSMC," the executive told the NAR.
 
"There is no rivalry between Apple and Intel so it's really likely that Apple could shift some orders there. The move is also in line with Washington's policy to encourage U.S. companies to make more products at home," the person said.

Samsung has demonstrated the EUV power source production target of 250W in process development. According to Low, the “magic number” for productivity with EUV is 1,500 wafers per day. Samsung has already exceeded 1,000 wafers per day and has a high degree of confidence that 1,500 wafers per day is achievable, Low said.

“We are confident that we are ready to bring [EUV] into production in 2018,” Low said. “This is no longer a concept roadmap item.”
 
Low said that Samsung, unlike some competitors, sees the 10nm node as a “long-lead node” that will provide customers with the performance and desired power consumption on leading edge designs for a considerable period of time.

• 8LPP (8nm Low Power Plus): 8LPP provides the most competitive scaling benefit before transitioning to EUV (Extreme Ultra Violet) lithography. Combining key process innovations from Samsung’s 10nm technology, 8LPP offers additional benefits in the areas of performance and gate density as compared to 10LPP.

• 7LPP (7nm Low Power Plus): 7LPP will be the first semiconductor process technology to use an EUV lithography solution. 250W of maximum EUV source power, which is the most important milestone for EUV insertion into high volume production, was developed by the collaborative efforts of Samsung and ASML. EUV lithography deployment will break the barriers of Moore’s law scaling, paving the way for single nanometer semiconductor technology generations.

• 6LPP (6nm Low Power Plus): 6LPP will adopt Samsung’s unique Smart Scaling solutions, which will be incorporated on top of the EUV-based 7LPP technology, allowing for greater area scaling and ultra-low power benefits.

• 5LPP (5nm Low Power Plus): 5LPP extends the physical scaling limit of FinFET structure by implementing technology innovations from the next process generation, 4LPP, for better scaling and power reduction.

• 4LPP (4nm Low Power Plus): 4LPP will be the first implementation of next generation device architecture – MBCFETTM structure (Multi Bridge Channel FET). MBCFETTM is Samsung’s unique GAAFET (Gate All Around FET) technology that uses a Nanosheet device to overcome the physical scaling and performance limitations of the FinFET architecture.

• FD-SOI (Fully Depleted – Silicon on Insulator): Well suited for IoT applications, Samsung will gradually expand its 28FDS technology into a broader platform offering by incorporating RF (Radio Frequency) and eMRAM(embedded Magnetic Random Access Memory) options. 18FDS is the next generation node on Samsung’s FD-SOI roadmap with enhanced PPA (Power/Performance/Area).
  

TSMC reported progress in 7 nm and extreme ultraviolet (EUV) lithography and bolstered a planar process that competes with fully depleted silicon-on-insulator at an annual event here. It also gave updates on its work in packaging and platforms for key market segments.

The process can deliver 20% greater density, 8–10% higher speeds, or 15–20% less power than its current N7 node. Compared to its 16FFC process, N7+ can enable 30% higher speed or 50% less power on an ARM A72 core, said Cliff Hou, vice president of R&D for design technology at TSMC.

Overall, the work of moving from N7 to N7+ should represent about a third of the effort of migrating to a new node, he added.

In packaging, TSMC said that it is working on a new variant of InFO, its wafer-level fab-out technique famously used in Apple’s latest A Series processors. InFO-MS will integrate logic and memory and is first being targeted for use with the latest high bandwidth memory (HBM2) in efforts among TSMC, Samsung, and SK Hynix.
 
Separately, Open-Silicon announced Tuesday that it has validated for use in system-in-package designs its HBM2 IP subsystem made using TSMC’s 16-nm process and its CoWoS 2.5-D chip stacking technology. It supports data rates up to 2 Gbits/second per pin. The company expects that a 7-nm version will hit 2.4 Gbits/s.

TSMC today announced that, following careful evaluation, the Company’s planned advanced 3nm fab will be located in the Tainan Science Park to fully leverage the company’s existing cluster advantage and the benefit of a comprehensive supply chain. TSMC recognizes and is grateful for the government’s clear commitments to resolve any issues, including land, water, electricity and environmental protection.

Intel will use cobalt in on the bottom two layers of its 10-nm interconnect to get a five- to ten-fold improvement in electromigration and a two-fold reduction in via resistance. It represents the first time that a chip maker has detailed plans to introduce cobalt — a brittle metal long considered a promising dielectric candidate — in a process, according to G. Dan Hutcheson, chairman and CEO of VLSI Research.

Both Intel and Globalfoundries had previously announced their newest process technologies. Intel's 10-nm node, first unveiled in March, features FinFETs with a 7-nm fin width at a 34-nm pitch and a 46-nm fin height made using self-aligned quadruple patterning (SAQP). Globalfoundries 7-nm node, first announced in September, uses SAQP to make fins and double patterning for metallization and boasts a 2.8-fold improvement in routed logic density and by up to 40% more performance or 55% lower power compared to its 14-nm process licensed from Samsung. Both processes support multiple voltage thresholds.

Extreme ultraviolet lithography (EUV) is set to enable 10-nm and 7-nm process nodes over the next few years, but significant work is still needed on photoresists to enable 5-nm chips, according to an analysis released at the Industry Strategy Symposium here

At the same time, EUV maker ASML announced that it shipped 10 EUV systems last year and will ship 20 to 22 more this year. The systems will have, or at least support, a 250-W laser light source needed to produce 125 wafers/hour.

Jones expects that ASML will ship another 70 systems in 2019–2020. That’s enough to support production nodes that he detailed in the works at Globalfoundries, Intel, Samsung, and TSMC.

ASML aims to boost the 145 wafers/hour throughput that it can get with its 250-W light source to 155 w/h in 2020. It has demonstrated a 375-W light source working in the lab, said Peter Jenkins, ASML’s vice president for corporate strategy and marketing, in a talk here.
The company’s pellicle passes through 83% of light today and withstands a 245-W light source over 7,000 wafer exposures. However, the most aggressive 7-nm nodes need a 90% transmission used with a 250-W or greater light source.

Researchers reported random defects appearing in extreme ultraviolet (EUV) lithography at 5-nm nodes. They are applying an array of techniques to eliminate them but, so far, see no clear solution.

A retired Intel lithographer predicted that engineers will be able to create 5-nm and even 3-nm devices by using two and three passes with an EUV stepper. But a rising tide of chip defects ultimately will drive engineers to new, fault-tolerant processor architectures such as neural networks, said Yan Borovodsky in a keynote at the event.

The random defects take many forms. Some are imperfectly made holes; others are tears in lines or shorts where two lines or two holes meet. Given their tiny dimensions, researchers sometimes spend days just to find them.

Another issue is that it’s unclear exactly what happens to resist materials when hit with EUV light. “It’s still unknown how many electrons are generated and what kinds of chemistries are created … we’re a little ways from a full understanding of the physics, so we’re doing more experiments,” said McIntyre, noting that researchers have tested as many as 350 combinations of resists and process steps.

In an interview, Borodovsky said that another factor that may be contributing to the 5-nm defects is a lack of homogeneity in the current EUV resist materials. Separately, he said that he supports work on direct e-beam writers because the complex phase-shift masks that EUV uses ultimately will balloon to eight times the price of today’s immersion masks.

Over the weekend, the NXE 3400B system delivered 140 wafers/hour with a 245-W light source integrated in a system at the company’s headquarters in the Netherlands. ASML aims to tune the light source to 250 W for throughput of 150 wafers/hour and ship it to customers before June for use on 7-nm process nodes.

ASML is considering a model 3400C that it could deliver in 2020 with additional improvements, boosting throughput to 155 WPH. Details of the system are still under discussion with the small handful of big chip vendors who would be its users.

The U.S. Department of Defense could be attracted by the promise of access to 3-nm chips as an expansion of the trusted foundry arrangement that GF acquired with IBM’s fabs in 2015. “This is important for national security and creating jobs … access to a secure domestic supply — we’ll work that angle,” said Caulfield.

I don’t know if 5 nm is enough to make a fabless company invest … they need something as defined as 3 nm to get full performance, but we’re still looking at what is the right investment for the next node.

“We don’t have the capacity … [and] we will be behind the leading 7-nm [foundry], but it costs more to be a leader than a fast follower,” in leading-edge nodes, he said.

GF also won’t try to follow rival TSMC in offering a variety of packages such as its 2.5D CoWoS and its InFO wafer-level fan-out for mobile processors.

Owner Mubadala invested in technology for the long term, but it wants to see a path to gains, he said.

The changes could address criticisms that GF has been slow to deliver on promises. For example, it was early to talk about fully depleted silicon-on-insulator as a low-cost alternative to FinFETs. But Samsung won the initial FD-SOI business, and now the two companies are competing to ramp customers.

It was four companies in a way with an AMD spinout in Dresden, the acquisitions of Chartered in Singapore and IBM in the U.S. … we started Malta before there was a company culture, so Malta was raised by wolves

Samsung Electronics laid out plans to bring to mass production in 2021 the architectural successor to FinFETS, gate-all-around (GAA) transistors, at the 3nm node. The South Korean giant also reaffirmed plans to begin 7nm production using extreme ultraviolet (EUV) lithography in the second half of this year at its annual foundry technology forum here Tuesday (May 22).

Samsung's proprietary GAA technology, known as multi-bridge-channel FET (MBCFET), has been in development since 2002, according to Ryan Sanghyun Lee, vice president of market for Samsung Foundry. MCBFET uses a nano-sheet device to enhance gate control, significantly improving the performance of the transistor, according to the company

"The Samsung roadmap was aggressive," said Kevin Krewell, I already knew they were moving fast on EUV, but this also sets a high bar."
 
But, Krewell added, "It's still a ways out and schedules can slip."

Samsung reiterated plans to begin using EUV lithography in mass production in the second half of this year with its 7nm Low Power Plus process. Samsung is expected to be the first chipmaker to put EUV — which the industry has been developing for many years — into commercial production. TSMC and Globalfoundries have announced plans to use EUV in commercial production starting in 2019.

Samsung's process technology roadmap also includes 5nm FinFET production in 2019 and 4nm FinFET production in 2020.

Fujitsu Semiconductor and UMC on Friday said that the latter will acquire 100% ownership of Mie Fujitsu Semiconductor (MIFS), a joint venture between two companies. The move essentially ends history of Fujitsu’s in-house manufacturing of microelectronics that began in 1956. Meanwhile, UMC will gain additional manufacturing resources in Japan, which somewhat boosts its competitive positions against key rivals.

Various sources report that the two MIFS fabs can produce from 28,000 to 40,000 300-mm wafers per month, which will be a nice addition to UMC’s 140,000 300-mm wafers per month. Meanwhile it is necessary to note that since the fabs have never been seriously upgraded, they cannot produce chips using 28 nm technology let alone FinFET fabrication processes. MIFS implied several years ago that 40 nm would be used for the next 20 to 30 years, though Fujitsu Semiconductor still decided to sell its aging asset to UMC.

UMC itself has been having troubles developing FinFET-based process technologies and barely processed several thousands of wafers using its 14 nm node in 2017. Therefore, expanding production capacities with mature product lines seems to be a bid to increase sales.
 
UMC’s acquisition of MIFS will enable the company to better compete against GlobalFoundries and TSMC for customers that require cheap and mature process technologies as well as for clients in Japan.

Sales in the global semiconductor-grade silicon wafer market are forecast to rise over 20% in 2018, after surging 20.8% in 2017, thanks to a continued rally in silicon wafer prices, according to Digitimes Research.
 
The average selling price (ASP) per square inch of silicon wafers came to US$0.86 in the first quarter of 2018 reaching the highest since 2013, said Digitimes Research. The ASP is expected to reach US$1 at the end of 2019, approaching the 2009-2011 level.

The supply of silicon wafers particularly that of 8- and 12-inch ones will remain tight for at least one to two years, according to Digitimes Research. Whether the tight supply will persist after 2020 will very much depend on the demand side. Industrial, IoT and automotive applications will play major drivers of demand for 8-inch wafers, while demand for 12-inch wafers will come from mainly the cloud storage and smartphone segments.

Dutch semiconductor equipment vendor  ASML said Wednesday it is on track to ship 20 extreme ultraviolet (EUV) systems in 2018 and expects to ship at least 30 more in 2019.

ASML shipped four EUV systems in the second quarter, one more than forecast, as logic customers prepare to ramp next-generation devices starting later this year, Wennink said.

Leading-edge semiconductor manufacturers include Samsung, Intel and TSMC are planning to use EUV in volume production beginning in the next year, though concerns remain about the availability of the EUV power source and other items in the EUV supply chain, including pellicles.
ASML says it has now demonstrated four-week availability of well above 85% on a number of its new NXE:3400B EUV systems and is executing several programs to improve consistent availability to over 90% in 2019.

In addition, TSMC has entered volume production of 7nm chips. Sales generated from 7nm process technology will account for about 10% of the foundry's total revenues in the third quarter, and the proportion will climb further to 20% in the fourth quarter, according to Wei.
 
TSMC has started taping out chips built using an enhanced 7nm node with EUV in July, which is ahead of schedule, Wei noted. The company is scheduled to move the node to volume production in the second quarter of 2019, Wei said.

To support this transition, GF is putting its 7nm FinFET program on hold indefinitely and restructuring its research and development teams to support its enhanced portfolio initiatives. This will require a workforce reduction, however a significant number of top technologists will be redeployed on 14/12nm FinFET derivatives and other differentiated offerings.

With sub-10nm node manufacturing requiring huge capex, a number of foundries have slowed down their investment pace while fabless chipmakers stick with 14/12nm products for cost reasons. Such scenario will likely turn a new leaf in the chip industry evolution, according to industry sources.

Fabless chip developers are aware that they have to spend big on sub-10nm chip development, and are concerned about whether such huge investment will pay off, the sources indicated.

Instead of developing the industry's first 7nm SoC chip, Qualcomm and MediaTek have both moved to enhance their upper mid-range offerings by rolling out respective new 14/12nm solutions, the sources noted. Questions have been raised about whether advancing to 7nm manufacturing node is necessary under the current circumstances, the sources said.

We shipped and recognized revenue for five EUV systems in the third quarter. In addition, we received five EUV orders. We expect to ship a total of 18 EUV systems this year. Our 2019 shipment plan is 30 systems as the first customers are about to start high volume production using EUV. We have made significant progress in the execution of our roadmap, accelerating the introduction of the higher-productivity system NXE:3400C, offering more than 155 wafers per hour. Shipment of this system is expected to start in the second half of 2019.

As described in a paper presented at this week’s IEEE International Electron Devices Meeting, the researchers modified a recently invented chemical-etching technique, called thermal atomic level etching (thermal ALE), to enable precision modification of semiconductor materials at the atomic level. Using that technique, the researchers fabricated 3-D transistors that are as narrow as 2.5 nanometers and more efficient than their commercial counterparts.

Microfabrication involves deposition (growing film on a substrate) and etching (engraving patterns on the surface). To form transistors, the substrate surface gets exposed to light through photomasks with the shape and structure of the transistor. All material exposed to light can be etched away with chemicals, while material hidden behind the photomask remains.

They used an alloyed semiconductor material, called indium gallium arsenide (or InGaAs), which is increasingly being lauded as a faster, more efficient alternative to silicon.

The device performed about 60 percent better than traditional FinFETs in “transconductance,” the researchers report. Transistors convert a small voltage input into a current delivered by the gate that switches the transistor on or off to process the 1s (on) and 0s (off) that drive computation. Transconductance measures how much energy it takes to convert that voltage.

IBM today announced an agreement with Samsung to manufacture 7-nanometer (nm) microprocessors for IBM Power Systems™, IBM Z™ and LinuxONE™, high-performance computing (HPC) systems, and cloud offerings.

"We are excited to expand our decade-long strategic relationship with IBM with our 7nm EUV process technology," said Ryan Lee, Vice President of Foundry Marketing at Samsung Electronics. "This collaboration is an important milestone for Samsung's foundry business as it signifies confidence in Samsung's cutting-edge high performance EUV process technology."

Samsung Electronics Co. won orders to produce desktop processor chips for Intel
 
“Samsung is expected to benefit from TSMC’s tight production schedule,” said Kim Yang-jae, analyst at KTB Investment & Securities. “More chip orders are likely to come from Intel and Qualcomm next year.”

Intel expects to be on 2 year cadence with its manufacturing process node technology, starting with 10nm in 2019 and moving to 7nm EUV in 2021, then a fundamental new node in each of 2023, 2025, 2027, 2029. This final node is what ASML has dubbed '1.4nm'. This is the first mention on 1.4nm in the context of Intel on any Intel-related slide. For context, if that 1.4nm is indicative of any actual feature, would be the equivalent of 12 silicon atoms across.

Beyond the NXE lines of machines will be the EXE:5000 series. What makes these machines different is that they are built for the equivalent of TSMC’s 3nm / Intel’s 5nm processes by using ‘High-NA’ technology, technically moving from 0.33 NA optics to 0.55 NA optics, which will help improve manufacturing features at smaller and smaller resolutions. It will be interesting to see if the speed of the High-NA EXE machines will be similar or better to the NXE machines. Based on ASML’s presentation, High-NA machines should be coming into the market by 2023, by which time EUV use should be extensive at the leading edge.

Another interesting EUV comment, I am hearing Samsung has a very high dose for their EUV process for critical layers and I have heard TSMC’s EUV dose is much lower with TSMC a >2x throughput advantage over Samsung> This is also consistent with reports that Samsung is having trouble getting enough wafers through their EUV tools. At another conference I saw an IBM presentation where they discussed developing the 5nm process with Samsung. They said that they turned up the EUV dose until they got good yield and transferred the process to Samsung with the idea that Samsung would then work on reducing the dose. It sounds like the process may have been rushed into production before reducing the EUV dose.

This earnings call marks the first time TSMC started disclosing actual information about its 3-nanometer (N3) node. C.C. Wei says the company’s N3 remains on track with risk production scheduled for 2021. TSMC is targeting volume production in the second half of 2022. The company says that after evaluating all the possible device technology options, it had decided to continue with FinFET for N3 due to its maturity, performance, and cost advantages.
 
In terms of density, TSMC says N3 will be another full node stride over N5 with a density improvement of 1.7x over N5. By our estimates, N3 should offer a cell-level density of just under 300 million transistors per millimeter square.

In terms of performance and speed, compared to N5, TSMC says N3 will provide 10-15% speed improvement at iso-power or 25-30% power reduction at iso-speed.

TSMC took the process density lead this year with their 5nm process. Depending on the exact timing of Intel’s 7nm process versus TSMC 3nm Intel may briefly regain a process density lead but TSMC will quickly pass them with their 3nm process with over 300 million transistors per millimeter squared !