Forum |  HardWare.fr | News | Articles | PC | Prix | S'identifier | S'inscrire | Aide | Shop Recherche
497 connectés 

 

 

 Mot :   Pseudo :  
 
 Page :   1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18
Page Suivante
Auteur Sujet :

News - Technologies, procédés, découvertes, actualité et situation

n°9243746
xixou2
Posté le 19-08-2014 à 21:30:10  profilanswer
 

Reprise du message précédent :

Invite_Surprise a écrit :

Samsung Now Mass Producing Industry’s Most Advanced DDR4, Using 20 Nanometer-class Process Technology
 
http://tof.canardpc.com/preview2/1 [...] 4abe5f.jpg
 

Citation :

With the introduction of these high-performance, high-density DDR4 modules, Samsung can better support the need for advanced DDR4 in rapidly expanding, large-scale data centers and other enterprise server applications.
 
Early market availability of the 4-gigabit (Gb) DDR4 devices, which use 20 nanometer (nm)-class* process technology, will facilitate demand for 16-gigabyte (GB) and 32GB memory modules. This compares to conventional DRAM of which 8GB modules using a 30nm-class* process technology are still commonplace.


 

Citation :

Editors’ Note: 20 nm-class means a process technology node somewhere between 20 and 30 nanometers, 30 nm-class means a process technology node somewhere between 30 and 40 nanometers, and 50 nm-class means a process technology node somewhere between 50 and 60 nanometers.



 
Commique, ça sera en vente le même jour, de cette année ^^


---------------
http://boincstats.com/signature/-1/user/839477/sig.png
mood
Publicité
Posté le 19-08-2014 à 21:30:10  profilanswer
 

n°9278779
Invite_Sur​prise
Racaille de Shanghaï
Posté le 23-09-2014 à 16:56:16  profilanswer
 

Intel Opens Door on 7nm, Foundry - EETimes
 

Citation :

“My day job is working on [research for a process to make] 7 nm [chips and] I believe there is a way without EUV,” said Intel fellow Mark Bohr, responding to a question after a talk on Intel’s new 14 nm process.


 

Citation :

“I am very interested in EUV [because it] could really help scaling and perhaps process simplification, reducing three or four masks to one in some cases,” Bohr said. “Unfortunately, it’s not ready yet -- the throughput and reliability are not there.”


 

Citation :

Intel already announced it has started making in volume chips using a 14 nm process at a lower cost per transistor than its prior 22 nm generation. It also said it is in development of a 10 nm process that it believes will deliver lower cost per transistor.


 

Citation :

In his most detailed talk to date, Sunit Rikhi, general manager of Intel’s custom foundry business, described the details of an end-to-end service that’s now more open than ever but still evolving.
Customers are currently using their own designs, supplemented with some IP blocks from Synopsys and Cadence. In the future, Intel will offer some IP, starting with an Atom core still in development.


 
http://tof.canardpc.com/view/c86f1d18-c399-4c0b-bfc6-8f651a5b116f.jpg http://tof.canardpc.com/view/acce0948-cf8b-40a4-85f1-2bcdfece3702.jpg http://tof.canardpc.com/view/b26eb982-4141-4e6e-833d-9847eeb18dec.jpg
 

Citation :

Most significantly, Intel is far along in testing a lower-cost alternative to 2.5D chip stacks it calls the Embedded Multi-Die Interconnect Bridge.
 
Unlike the 2.5D process, EMIB does not lay dies side-by-side on large silicon interposers, connecting them with through silicon vias (TSVs). Instead it uses a more conventional kind of flip chip process with metal bump interconnects inside a package.


 

n°9280834
Invite_Sur​prise
Racaille de Shanghaï
Posté le 25-09-2014 à 13:48:02  profilanswer
 

TSMC Delivers First Fully Functional 16FinFET Networking Processor - TPU
 

Citation :

TSMC today announced that its collaboration with HiSilicon Technologies Co, Ltd. has successfully produced the foundry segment's first fully functional ARM-based networking processor withFinFET technology. This milestone is a strong testimonial to deep collaboration between the two companies and TSMC's commitment to providing industry-leading technology to meet the increasing customer demand for the next generation of high-performance, energy-efficient devices.
 
TSMC's 16FinFET process promises impressive speed and power improvements as well as leakage reduction. All of these advantages overcome challenges that have become critical barriers to further scaling of advanced SoC technology. It has twice the gate density of TSMC's 28HPM process, and operates more than 40% faster at the same total power, or reduces total power over 60% at the same speed.


 

Citation :

TSMC's 16FinFET has entered risk production with excellent yields after completing all reliability qualifications in November 2013. This paves the way for TSMC and customers to engage in more future product tape-outs, pilot activities and early sampling.
 
"We are delighted to see TSMC's FinFET technology and CoWoSsolution successfully bringing our innovative designs to working silicon," said HiSilicon President Teresa He."This industry's first 32-core ARM Cortex-A57 processor we developed for next-generation wireless communications and routers is based on the ARMv8 architecture with processing speeds of up to 2.6GHz.

n°9411595
Invite_Sur​prise
Racaille de Shanghaï
Posté le 05-02-2015 à 13:22:47  profilanswer
 

Nvidia Newest Samsung Foundry Customer For 14nm Process, After Apple And Qualcomm - Tom's Hardware
 

Citation :

Park Yu-ak, an analyst at Meritz Securities, said, "Global AP makers are likely to focus on lowering the cost of production this year in order to offset a decline in AP prices." He added, "Samsung's system semiconductor business is going to mass produce and supply chips to Apple, Qualcomm, and Nvidia starting in the second quarter of this year. As a result, the Korean tech giant is projected to exhibit stellar performance."


 
Source
 
Cela concernerait à priori seulement Tegra mais c'est un changement vraiment important pour nVidia.
Si Samsung peut rivaliser avec TSMC, cela promet une bonne concurrence entre les 2 fondeurs et c'est une excellente nouvelle.

n°9459560
Invite_Sur​prise
Racaille de Shanghaï
Posté le 08-04-2015 à 20:55:42  profilanswer
 

TSMC Processes Galore - SemiWiki
 

Citation :

Today was TSMC's 2015 North American Technology Symposium. They talked about a lot of things but perhaps the most important was that they gave a lot of details of new processes, new fabs, and volume ramps.


 

Citation :

16FF+
This is the second generation of TSMC's 16FF process. Volume production will be mid-2015, which is just one-year after 20nm volume production started. TSMC already has over a dozen tape-outs and expects to have over 50 by the end of 2015. The process has 10% better performance than competitors and 50% less power than 20nm.


 

Citation :

10FF
TSMC said this is ahead of schedule. They have already built and yielded a 256Mb SRAM. The density of 10nm will be 2.1x that of 16nm node partially due to a new local interconnect layer and partially because they are using self-aligned spacer (aka SADP or SIT) on the metal. SRAM cell shrinks by 0.46 to 0.49. Risk production will be 4Q2015. Test chip based on ARM Cortex A-57 taped out 2 weeks ago. There is a 19% speed gain or 38% power reduction based on this test chip.


 

Citation :

16FFC
This is, I believe, a process newly announced today. It is a more compact version of 16FF+ aimed at the consumer marketplace. Same design rules. Simpler process, tighter process corners. Power is reduced by over 50% and the pricing is cost-competitive for mainstream markets (which I take as meaning it is cheaper than 28nm for the same design). Voltage is 0.55V. Version 1.0 collateral will be available 1Q2016 with customer tape-outs in 2H2016.

n°9459712
Gigathlon
Quad-neurones natif
Posté le 09-04-2015 à 00:04:33  profilanswer
 

Pas moyen de retrouver la densité de défauts de GloFo, mais il me semble bien qu'ils avaient annoncé moins que les "0.05 et même parfois 0.03/cm²" cités... pour l'introduction.


Message édité par Gigathlon le 09-04-2015 à 00:05:22
n°9615165
Invite_Sur​prise
Racaille de Shanghaï
Posté le 22-09-2015 à 21:25:40  profilanswer
 

Dans une interview à EETimes, le CEO de GloFo lève le voile sur la stratégie à venir du fondeur :
 

Citation :

EE Times: When will the first chip (based on Globalfoundries’ 22nm FD-SOI) become commercially available?
 
Jha: We are expecting the production tape-out to be in the second half of 2016.


 

Citation :

EE Times: For 14nm node, Globalfoundries depended on the technology licensed from Samsung. What’s your plan for 10nm and 7nm? Will you develop your own technologies?
 
Jha: We’re developing our own technologies for the next nodes. The whole point of the IBM Microelectronics business acquisition is to leverage IBM’s technologists and technology to accelerate our own development of leading-edge process technologies.


 

Citation :

EE Times: FinFET promoters already have a roadmap for 10nm and 7nm. What’s the FD-SOI roadmap beyond 22nm?
 
Jha: We have an FD-SOI roadmap that also scales. We’re currently exploring with our partners if we should use a different tool set for the next node. If it turns out to be different, we’ll do the next-node FD-SOI production in Malta, NY, while Dresden remains focused on 22nm FDX.


 
http://www.eetimes.com/document.as [...] e_number=2

n°9615185
Invite_Sur​prise
Racaille de Shanghaï
Posté le 22-09-2015 à 21:45:52  profilanswer
 

Un autre article intéressant aussi chez EETimes mais traitant de TSMC :
 

Citation :

The road map suggests TSMC could leapfrog Intel to producing 10nm chips, although naming conventions for nodes these days hide the underlying details of the processes. What's more clear is TSMC has gotten off to a slow start with its 16nm FinFET process with close partners such as Xilinx saying they have taped out but not yet shipped their first chip in the process. Xilinx also plans to skip TSMC’s 10mn process in favor of its 7nm node, a significant choice given Xilinx typically acts as a logic driver for new TSMC nodes.


 

Citation :

TSMC has made a working SRAM at 7nm, Sun reported. The node should deliver 40-45% less area and either 10-15% higher speeds or 25-30% lower power than the 10nm node, he said.
 
The foundry expects to start “risk” production for 7nm in the first quarter of 2017. It is developing the process for existing immersion steppers, Sun told EE Times. Nevertheless, Sun reported progress with EUV systems now running at 90W and expected to have throughput as high as 125 wafers/hour later this year.


 
http://www.eetimes.com/document.as [...] e_number=1

n°9929193
Invite_Sur​prise
Racaille de Shanghaï
Posté le 29-08-2016 à 18:30:12  profilanswer
 

Intel to start manufacturing Apple SoCs in 2018? - Asia Nikkei/DVHardware

Citation :


"TSMC could face tough competition as soon as 2018 or 2019 as Intel is likely to gain orders from Apple by then," Samuel Wang, a veteran semiconductor analyst at research company Gartner, told the Nikkei Asian Review. "Intel has begun to engage with Apple and it aims to grab one or two top-tier customers from TSMC."


 

Citation :

A senior Taiwanese chip industry executive shared Wang's views. "Intel is definitely the most formidable challenger for TSMC," the executive told the NAR.
 
"There is no rivalry between Apple and Intel so it's really likely that Apple could shift some orders there. The move is also in line with Washington's policy to encourage U.S. companies to make more products at home," the person said.


 
Via DVHardware
 
 

n°9929195
nicolas_ya​d
Spoons made me fat
Posté le 29-08-2016 à 18:31:01  profilanswer
 

[:drapal]

mood
Publicité
Posté le 29-08-2016 à 18:31:01  profilanswer
 

n°9937196
Invite_Sur​prise
Racaille de Shanghaï
Posté le 06-09-2016 à 15:27:14  profilanswer
 
n°9938984
Klivan
Ach... Encore raté...
Posté le 08-09-2016 à 15:35:34  profilanswer
 

:hello:  
 
Peut-être un peu à côté de la plaque, mais ce topic me paraissait le plus adapté: est-ce que quelqu'un saurait où je pourrais trouver les capacités de production par node? Et encore mieux, leur évolution dans le temps?
 
Many thanks  :jap:


---------------
We are the knights who say : Ni! / 'Bye Julfisher :(
n°9939093
xixou2
Posté le 08-09-2016 à 17:37:13  profilanswer
 

Klivan a écrit :

:hello:

 

Peut-être un peu à côté de la plaque, mais ce topic me paraissait le plus adapté: est-ce que quelqu'un saurait où je pourrais trouver les capacités de production par node? Et encore mieux, leur évolution dans le temps?

 

Many thanks :jap:


capacite de production par rapport a quoi ?


---------------
http://boincstats.com/signature/-1/user/839477/sig.png
n°9939884
Klivan
Ach... Encore raté...
Posté le 09-09-2016 à 15:26:45  profilanswer
 

En wafers par mois, en gros j'aimerais pouvoir comparer les cycles de vie des différents process à travers le temps (adoption, croissance, décroissance).
 
J'ai essayé de regarder dans les rapports financiers de TSMC, mais ils ne divulguaient que les revenus issus de ces procédés, et pas les capacités de production. Et si les process de pointe sont logiquement développés par un nombre limité d'acteurs, ce qui rend la collecte des données moins ardue, il me semble que le 28nm par exemple est toujours en croissance... mais je suis loin de connaître tous les acteurs qui l'utilisent  [:transparency]


---------------
We are the knights who say : Ni! / 'Bye Julfisher :(
n°9940614
xixou2
Posté le 10-09-2016 à 15:24:27  profilanswer
 

je sais que pour le 10 nm ca doit se faire en quatre passes et que ca coute cher et apporte des risques de decallages a la gravure. la lumiere UV sera bientot bien geree et la on pourra graver petit avec rapidite et sans soucis.


---------------
http://boincstats.com/signature/-1/user/839477/sig.png
n°10155745
Invite_Sur​prise
Racaille de Shanghaï
Posté le 26-05-2017 à 19:56:03  profilanswer
 

Samsung Targets 4nm in 2020 - EETimes
 

Citation :

Samsung has demonstrated the EUV power source production target of 250W in process development. According to Low, the “magic number” for productivity with EUV is 1,500 wafers per day. Samsung has already exceeded 1,000 wafers per day and has a high degree of confidence that 1,500 wafers per day is achievable, Low said.


 

Citation :

“We are confident that we are ready to bring [EUV] into production in 2018,” Low said. “This is no longer a concept roadmap item.”
 
Low said that Samsung, unlike some competitors, sees the 10nm node as a “long-lead node” that will provide customers with the performance and desired power consumption on leading edge designs for a considerable period of time.


 

Citation :

  • 8LPP (8nm Low Power Plus): 8LPP provides the most competitive scaling benefit before transitioning to EUV (Extreme Ultra Violet) lithography. Combining key process innovations from Samsung’s 10nm technology, 8LPP offers additional benefits in the areas of performance and gate density as compared to 10LPP.

 

  • 7LPP (7nm Low Power Plus): 7LPP will be the first semiconductor process technology to use an EUV lithography solution. 250W of maximum EUV source power, which is the most important milestone for EUV insertion into high volume production, was developed by the collaborative efforts of Samsung and ASML. EUV lithography deployment will break the barriers of Moore’s law scaling, paving the way for single nanometer semiconductor technology generations.

 

  • 6LPP (6nm Low Power Plus): 6LPP will adopt Samsung’s unique Smart Scaling solutions, which will be incorporated on top of the EUV-based 7LPP technology, allowing for greater area scaling and ultra-low power benefits.

 

  • 5LPP (5nm Low Power Plus): 5LPP extends the physical scaling limit of FinFET structure by implementing technology innovations from the next process generation, 4LPP, for better scaling and power reduction.

 

  • 4LPP (4nm Low Power Plus): 4LPP will be the first implementation of next generation device architecture – MBCFETTM structure (Multi Bridge Channel FET). MBCFETTM is Samsung’s unique GAAFET (Gate All Around FET) technology that uses a Nanosheet device to overcome the physical scaling and performance limitations of the FinFET architecture.

 

  • FD-SOI (Fully Depleted – Silicon on Insulator): Well suited for IoT applications, Samsung will gradually expand its 28FDS technology into a broader platform offering by incorporating RF (Radio Frequency) and eMRAM(embedded Magnetic Random Access Memory) options. 18FDS is the next generation node on Samsung’s FD-SOI roadmap with enhanced PPA (Power/Performance/Area).


http://news.samsung.com/global/sam [...] own-to-4nm

n°10163780
Invite_Sur​prise
Racaille de Shanghaï
Posté le 09-06-2017 à 14:39:30  profilanswer
 
n°10164070
xixou2
Posté le 09-06-2017 à 22:28:29  profilanswer
 
n°10164134
BIERMAN
16 YEARS HFR AWAŸ W/O SEQUEL¤§
Posté le 10-06-2017 à 02:27:05  profilanswer
 

Pourquoi faire si le 5 est mieux
Moi, je partirai direct sur le 10
Je serai tranquille longtemps :o
C'est pas comme si à cause de ça, les gens devront changer dans +/-~1&1/2 an leur matériel qu'il vont acheter bientôt (tant chez AMD qu'Intel) [:jocefuck]


Message édité par BIERMAN le 10-06-2017 à 02:28:54

---------------
▬© CABASSE ▬© AMD Radeon™ Crimson ReLive ▬© CM AM3+ 100% &- ▬© o/c C2D&Q i7 matuer† ▬® F3€&ack
n°10233703
Invite_Sur​prise
Racaille de Shanghaï
Posté le 15-09-2017 à 16:35:07  profilanswer
 

TSMC Updates its Silicon Menu - EETimes
 

Citation :

TSMC reported progress in 7 nm and extreme ultraviolet (EUV) lithography and bolstered a planar process that competes with fully depleted silicon-on-insulator at an annual event here. It also gave updates on its work in packaging and platforms for key market segments.


 

Citation :

The process can deliver 20% greater density, 8–10% higher speeds, or 15–20% less power than its current N7 node. Compared to its 16FFC process, N7+ can enable 30% higher speed or 50% less power on an ARM A72 core, said Cliff Hou, vice president of R&D for design technology at TSMC.


Citation :

Overall, the work of moving from N7 to N7+ should represent about a third of the effort of migrating to a new node, he added.


Citation :


In packaging, TSMC said that it is working on a new variant of InFO, its wafer-level fab-out technique famously used in Apple’s latest A Series processors. InFO-MS will integrate logic and memory and is first being targeted for use with the latest high bandwidth memory (HBM2) in efforts among TSMC, Samsung, and SK Hynix.
 
Separately, Open-Silicon announced Tuesday that it has validated for use in system-in-package designs its HBM2 IP subsystem made using TSMC’s 16-nm process and its CoWoS 2.5-D chip stacking technology. It supports data rates up to 2 Gbits/second per pin. The company expects that a 7-nm version will hit 2.4 Gbits/s.


 

n°10241846
Invite_Sur​prise
Racaille de Shanghaï
Posté le 29-09-2017 à 13:27:30  profilanswer
 

TSMC to build 3nm production plant in Taiwan - TSMC
 

Citation :

TSMC today announced that, following careful evaluation, the Company’s planned advanced 3nm fab will be located in the Tainan Science Park to fully leverage the company’s existing cluster advantage and the benefit of a comprehensive supply chain. TSMC recognizes and is grateful for the government’s clear commitments to resolve any issues, including land, water, electricity and environmental protection.

mood
Publicité
Posté le   profilanswer
 

 Page :   1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18
Page Suivante

Aller à :
Ajouter une réponse
 

Sujets relatifs
News PC quelques questionPanne a8nsli deluxe (avis sur la situation)
ma news moboAvis - Conseils sur news Config...
news seagate 7200.10 250go qui a disparu du bios...[RCH/ACH]conseil achat news pc pour joueur
PC Horizontal /Vertical--> Marche / marche pas ..la suite[Topic unique] HD 3870x2
News configplate-forme STAFF IPX de AFFIXE Technologies
Plus de sujets relatifs à : News - Technologies, procédés, découvertes, actualité et situation



Copyright © 1997-2016 Hardware.fr SARL (Signaler un contenu illicite) / Groupe LDLC / Shop HFR