Globalfoundries will install an EUV tool from ASML in the second half of 2012 and will be using EUV in volume production by 2014 or 2015. With risk production set to begin in the second half of 2012, the company is expected to deliver 22- and 20-nm technology to customers for product introduction in 2013.  So until the EUV tool is delivered, Globalfoundries may resort to only offering one option at 20-nm: 193-nm immersion with double patterning.

As expected, the 28nm SOC process has excellent analog/RF characteristics, and the authors claim to match the performance of existing 28nm process technologies that use a poly-silicon based gate oxide. Varactors (i.e. variable capacitors), which are used for various wireless applications, in particular saw a huge improvement with respect to 45nm. The authors indicate that the high-k gate dielectric enabled substantially thinner gate oxides and improved the tuning ratio by a factor of 20 (versus 45nm). Figure X above shows the varactor Q factor versus frequency, achieving ~38 at 4GHz and ~15 at 10GHz.  
 
In addition to providing a number of device level metrics, the IBM team also provided some insight into the benefits of 28nm for a low power microprocessor. They compared an ARM Cortex-R4F on their 45nm process to the newer 28nm node and achieved a 2.4X area reduction. (lien)

The overall thrust of TSMC’s presentation was that they believe they can provide excellent alternatives to a high-k/metal gate process while using a conventional gate stack for low power devices. The key was creating two families of logic transistors, and selectively optimizing one to try and match HKMG performance at low voltage, and providing a second higher voltage family with extremely low power. The net result is that TSMC claims they provide a 25-40% speed gain or 30-50% active power reduction (or some linear combination thereof) compared to their previous 45nm process.

Les acteurs européens du semiconducteur étaient réunis à l’occasion d’un colloque sur les technologies en cours de développement. Un débat sur l’utilité d’investir dans les wafers de 450 mm a grandement divisé les membres présents.
Investir dans le 450 mm ou pas
 
Les grands noms étaient présents. NXP, STMicroelectronics et même Globalfoundries qui disposent d’usines en Ireland et en Allemagne. Pour rappel, les wafers de 450 mm sont censés accroître les rendements et baisser les coûts de production en permettant de produire plus de puces d’un seul coup. Le problème est que cette technologie coûte aujourd’hui très cher. En plus d’obtenir des galettes qui sont plus difficiles à produire, il faut de nouvelles machines onéreuses (cf. « Miniaturisation des transistors et agrandissement des wafers : comprendre les enjeux technologiques »)
 
De nombreux acteurs estiment donc que l’Europe n’a pas à investir l’argent des contribuables dans la recherche et le développement d’une gravure sur ce type de wafer. Selon eux, il est préférable de mettre cet argent sur les MEMS ou les dérivés du CMOS.
 
La question est d’une importance capitale, car une erreur de jugement poussera la production de semiconducteurs en dehors de l’Europe, ce qui aura forcément des conséquences néfastes pour les pays du vieux continent et leurs fondeurs.
De la réelle utilité du 450 mm
 
Jean-Marc Chery, directeur chez le franco-italien STMicroelectronics, semble avoir résumé la situation. Selon lui, il faut d’abord se demander où va le marché. S’il se dirige vers les produits mobiles, alors le 10 nm sur des wafers de 300 mm est suffisant pour apporter les transistors nécessaires. En clair, il privilégie la finesse de gravure qui a un impact direct sur les performances de la puce, au détriment du le 450 mm qui n’influe que les coûts de production, mais qui aujourd’hui ne garantit pas forcément une baisse du prix du transistor.
 
Cette position semble être aussi tenue par Intel qui a annoncé la construction d’une nouvelle usine le mois dernier (cf. « Fab 42 : la nouvelle usine d'Intel à 5 milliards $ ») qui va graver en 14 nm, qui sera ouverte en 2013, mais qui n’utilisera que des wafers de 300 mm. Un responsable d’Intel Ireland a d’ailleurs pris la parole, mais est resté très prudent sur le sujet, tout comme le représentant de Globalfoundries.
 
Concrètement, ce mouvement de réticence semble confirmer le retard du 450 mm au profit des nouveaux processus de fabrication toujours plus complexes. Intel devrait être un des premiers sur cette technologie, car sa position lui permet certaines largesses, mais nous n’anticipons pas une adoption massive du 450 mm dans les cinq prochaines années.

(Nanowerk News) Magnetic Random Access Memories (MRAM) are the most important new modules on the market of computer storage devices. Like the well known USB-sticks, they store information into static memory, but MRAM offer short access times and unlimited writing properties. Commercial MRAMs have been on the market since 2005. They are, however, still slower than the competitors they have among the volatile storage media.
 
An invention made by the Physikalisch-Technische Bundesanstalt (PTB) changes this situation: A special chip connection, in association with dynamic triggering of the component, reduces the response from - so far - 2 ns to below 500 ps.  This corresponds to a data rate of up to 2 GBit (instead of the approx. 400 MBit so far)( Cela correspond à un taux de données allant jusqu'à 2 Gbits/s (au lieu de env. 400 Mbits/s à ce jour)). Power consumption and the thermal load will be reduced, as well as the bit error rate. The European patent is just being granted this spring; the US patent was already granted in 2010. An industrial partner for further development and manufacturing such MRAMs under licence is still being searched for. arf pas cool ça !!
 

Electron-microscopic recording of an MRAM storage cell
 
Fast computer storage chips like DRAM and SRAM (Dynamic and Static Random Access Memory) which are commonly used today, have one decisive disadvantage: in the case of an interruption of the power supply, the information stored on them is irrevocably lost. The MRAM promises to put an end to this. In the MRAM, the digital information is not stored in the form of an electric charge, but via the magnetic alignment of storage cells (magnetic spins). MRAMs are very universal storage chips because they allow - in addition to the non-volatile information storage - also faster access, a high integration density and an unlimited number of writing and reading cycles.
 
However, the current MRAM models are not yet fast enough to outperform the best competitors. The time for programming a magnetic bit amounts to approx. 2 ns. Whoever wants to speed this up, reaches certain limits which have something to do with the fundamental physical properties of magnetic storage cells: during the programming process, not only the desired storage cell is magnetically excited, but also a large number of other cells. These excitations – the so-called magnetic ringing – are only slightly attenuated, their decay can take up to approx. 2 ns, and during this time, no other cell of the MRAM chip can be programmed.
 
As a result, the maximum clock rate of MRAM is, so far, limited to approx. 400 MHz. Until now, all experiments made to increase the velocity have led to intolerable write errors. Now, PTB scientists have optimized the MRAM design and integrated the so-called ballistic bit triggering which has also been developed at PTB. Here, the magnetic pulses which serve for the programming are selected in such a skilful way that the other cells in the MRAM are hardly magnetically excited at all. The pulse ensures that the magnetization of a cell which is to be switched performs half a precision rotation (180°), while a cell whose storage state is to remain unchanged performs a complete precision rotation (360°). In both cases, the magnetization is in the state of equilibrium after the magnetic pulse has decayed, and magnetic excitations do not occur any more.
 
This optimal bit triggering also works with ultra-short switching pulses with a duration below 500 ps. The maximum clock rates of the MRAM are, therefore, above 2 GHz. In addition, several bits can be programmed at the same time which would allow the effective write rate per bit to be increased again by more than one order. This invention allows clock rates to be achieved with MRAM which can compete with those of the fastest volatile storage components.
 
Source: Physikalisch-Technische Bundesanstalt (PTB)

VESA® Issues Updated Embedded DisplayPort® (eDP) Standard Version 1.3

(Version 1.3 created to save system power and further extend device battery life)
 
Newark, CA, Feb. 7, 2011 – The Video Electronics Standards Association (VESA) has announced a new version of the Embedded DisplayPort Standard (eDP™).  eDP is a companion standard to the DisplayPort interface designed for embedded display applications, including notebook PCs, tablets, netbooks and all-in-one desktop PCs. eDP v1.3 includes a new Panel Self-Refresh (PSR) feature that was developed to save system power and further extend battery life in portable PC systems.
 
Industry market trends indicate that eDP is slated to replace LVDS (Low-Voltage Differential Signaling), the previous standard for LCD panel inputs. In December 2010, Intel and AMD announced that by 2013, the two companies will no longer support LVDS in favor of scalable and lower power digital interfaces, such as DisplayPort. Leading PC manufacturers Dell, Lenovo, Samsung and LG Display announced similar plans to phase out legacy technologies in the coming years.
 
With eDP now even more capable of saving total device power and battery life, industry analysts believe it is the ideal replacement for LVDS. “As OEMs prepare to retire legacy technologies, such as LVDS, eDP offers a feature-rich replacement that is cost effective and ready for high volume implementation,” says Brian O’Rourke, principal analyst, In-Stat. “This, combined with the growing demand for high performance mobile devices, suggests eDP will continue to gain traction among PC OEMs.”
 
The eDP v1.3 Standard adds clarity on how to use the new 5.4, Gb/s DisplayPort main link data rate, also known as HBR2 (High Bit Rate 2). eDP v1.3 is now available for purchase from VESA and is provided free of charge to VESA member companies. Portable PC devices utilizing the new eDP v1.3 PSR feature are expected to become available for purchase as early as 2012.

Heureusement pour AMD, la solution pourrait (face aux problèmes du HDMI 1.4a) venir du... DisplayPort, que la marque supporte de manière plutôt active. Sans la moindre licence à payer au niveau des constructeurs, cette connectique dispose dans sa version 1.2 d'une bande passante quasiment doublée par rapport à l'HDMI 1.4 et permettra le passage à la 3D en 1080p120, voire même en 2560x1600 @ 120 Hz. Malheureusement, et pour une raison que nous n'arrivons pas à comprendre, les industriels se focalisent sur l'HDMI, qui nécessite de payer une licence mais qui est plus connu au niveau du grand public. Une solution qui n'a pourtant aucune viabilité pour le jeu 3D sur PC tant elle limite les usages, ce que l'on ne peut que regretter.

Look at the Products page on the Consumer site at http://www.displayport.org. There are many LCD monitors with DisplayPort and some in the low $200 US dollar price range. For computers with DisplayPort see same. AMD graphics cards with DisplayPort are available for any desktop PC.

There are many DP to HDMI adaptors to solve this problem.

C’est une question intéressante, puisque cette mise à jour, si elle est bien prise en compte par la nouvelle génération d’ATI, permettra de faciliter l’usage de la technologie Eyefinity. En effet, l’un des principaux avantages de la nouvelle norme 1.2 du DisplayPort est le doublement de la bande passante par sortie. Il devrait ainsi être possible de raccorder directement, via un seul câble, jusqu’à 4 écrans en 1920 x 1200. 2 en 2560 x 1600, avec un rafraichissement maximal de l’image à 60 Hz. Grâce à cela AMD pourrait très facilement proposer de l’Eyefinity 6 sur ses HD 6870 qui n’auraient plus besoin de 6 sorties. Simplement deux DisplayPort de cette norme suffiraient.

The HDMI 1.4a specification, which boasts a maximum TMDS throughput of 10.2 Gb/s, you can either game in stereo at 720p maxing out at 60 frames per second per eye, or you can game at 1080p with up to 24 frames per second per eye. That's actually pretty severe, considering we've been playing around with 5760x1080 using 3D Vision Surround and dual-link DVI connectors (each display running at 1920x1080). AMD says it'll transcend the shackles of HDMI 1.4a next year sometime when monitor vendors begin incorporating DisplayPort 1.2. A peak effective bandwidth of 17.28 Gb/s is enough to enable 1080p at 60 frames per eye.

DisplayPort 1.2 is one capability that AMD did add, enhancing bandwidth over the interface, integrating support for high-bit rate audio alongside video, and defining compatibility with the next generation of 120 Hz 3D monitors. Moreover, DisplayPort 1.2 is able to drive multiple displays from each output. That's right. DisplayPort displays can now be daisy-chained. That is to say a single DisplayPort output can use a Multi-Stream Transport (MST) hub to split off into multiple DP/VGA/DVI/HDMI displays of your choosing. Special Eyefinity edition cards are no longer necessary for six-monitor use.

If you want to watch Blu-ray 3D, you’re going to have to pay for Blu-ray 3D playback software, regardless of the graphics card. With an Nvidia card, you need to purchase the $40 3DTV Play driver from Nvidia at least or a $200 3D Vision kit at most. The interesting part is that AMD has actually bypassed any proprietary expense, so Blu-ray 3D playback is that much cheaper on Radeon cards.

DisplayPort 1.2 introduced a huge selection of new features: DisplayPort now boasts a maximum bitrate of 21.6 gigabits per second (doubled over its 1.1a spec), bi-directional data transfer via Display USB at 720 megabits per second, and standard Ethernet data transfer as well. It’s essentially audio, video, USB and Ethernet rolled into one, if you’re using a DisplayPort 1.2-capable machine. DisplayPort can handle a single display resolution up to 3840x2400, or a single Full HD 3D display at 2560x1600.

DisplayPort is even better when it comes to multi-monitor setups--it supports daisy chaining, meaning any DisplayPort 1.2 monitor with In and Out ports can be connected with multiple cables running off one computer output. 1.2 supports two monitors running at 2560x1600 or four monitors at up to 1920x1200.

DisplayPort supports DRM standards such as HDCP just like HDMI does--with port adapters, DisplayPort can even carry HDMI, DVI, or VGA signals. Apple has adopted DisplayPort into its systems, which certainly puts a big name behind the technology

Le constructeur Renesas Electronics vient d’annoncer deux nouveaux contrôleurs USB SuperSpeed, les µPD720201 et µPD720202. Ces deux contrôleurs USB 3.0 de troisième génération sont censés être à la fois plus rapides et plus économes en énergie que les modèles actuels.
 
En pratique, ces deux puces permettraient d’améliorer de 40% les performances en écriture, tandis qu’elles consommeraient 90% d’énergie en moins (soit 4,5mW) lorsqu’elles sont inactives. Cerise sur le gâteau, les µPD720201 et µPD720202 sont plus compacts (de 50% environ) que les contrôleurs actuels.
 
La production de masse de ces contrôleurs USB 3.0 devrait débuter vers le mois de septembre 2011, ce qui signifie qu’ils pourraient être présents sur les futures cartes mères LGA 2011 d’Intel.

''... Rumblings about Apple’s decision to shift A5 processor orders to TSMC from Samsung have gathered steam,'' said Steven Pelayo, an analyst with HSBC, in a new report. ''While unconfirmed, we believe cooperation is inevitable considering TSMC’s capacity and technological advantages, as well as a lack of potential interest conflicts ...''

Des chercheurs japonais ont réussi à dépasser la limite de 100 Tb/s sur une fibre optique en changeant le modulateur. Ils ont franchi une limite que l’on pensait physiquement incassable.
 
En 2001, les scientifiques ont atteint 100 Tb/s sur une fibre optique et ont décrété qu’il s’agissait de la limite physique sur ce support. Le diamètre d'une fibre est de seulement 9 µm, mais la densité énergétique est extrêmement importante. Le signal transmis sous forme de photons est détérioré par les hautes températures et la puissance importante au coeur de la fibre. Les chercheurs avaient donc conclu que ces limites empêchaient une transmission supérieure à 100 Tb/s.
 
Des universitaires japonais de l’Institut national des technologies de l’information et la communication ont néanmoins réussi à atteindre 109 Tb/s et affirme qu’il sera possible de dépasser l’ancienne limite de plus de 1 000 fois. Pour arriver à leurs fins, ils utilisent grossièrement un système multicore au sein d’une même fibre. Au lieu d’avoir un lien photonique, une fibre va en véhiculer plusieurs. Cette technique n’est pas nouvelle, mais pour la première fois, les chercheurs ont réussi à éviter que les cores interfèrent les uns avec les autres, grâce à un modulateur ultrarapide qui a porté le signal sur 16,8 km sur sept cores différents.
 
Le grand avantage est qu’il est possible de profiter de cette technologie sans avoir à remplacer le câble. Reste maintenant à voir si les chercheurs pourront sortir ce modulateur de leur laboratoire.

With the impact of Japan's massive earthquake disrupting production at silicon wafer supplier Shin-Etsu Handotai (SEH), major pure-play foundry chipmakers Taiwan Semiconductor Manufacturing Company (TSMC) and United Microelectronics Corporation (UMC) have both said that they are capable of activating alternatives if necessary.
 
SEH's parent company Shin-Etsu Chemical has revealed that operations at several production sites, including SEH's Shirakawa plant in Nishigo Village, Fukushima Prefecture, remain closed due to the quake's impact which has shutdown electric power supply in the area. A restart of operations can only begin after a safety inspection of equipment and the facilities, Shin-Etsu said, without disclosing any timeframe.
 
SEH's monthly 12-inch wafer capacity is estimated at about 1.2 million units, of which 800,000 are produced at the Shirakawa plant. Market observers have expressed concern that a supply shortage of 12-inch blank silicon wafers could surface.
 
Topco Scientific, a major distributor for SEH in Taiwan, has responded saying that it is still waiting for further updates from the supplier. Due to disruptions in power following the quake, operations at SEH's Shirakawa plant have not yet been restored, Topco indicated.
 
TSMC noted that the company has reached its supply partners in Japan, and information provided so far indicates that TSMC's orders placed earlier should not be impacted. TSMC added that wafer inventory remains at a sufficient level.
 
TSMC reportedly also sources silicon wafers from non-Japan-based suppliers including MEMC Electronic Materials, Siltronic and Formosa Sumco Technology (FST).
 
UMC indicated that in addition to Japan's SEH and Sumco, the foundry has also secured silicon wafer supplies from MEMC and Siltronic. Meanwhile, SEH has production sites overseas that help the company ease any supply tightness. UMC estimated that the impact on its suppliers will not be significant.
 
In other news, normal business operations at UMC Japan (UMCJ) have resumed already, UMC said. The wholly-owned subsidiary suffered minimal impact from the earthquake.

"We can say with 100 percent certainty that this is a Samsung-made chip," said Allan Yogasingam, a technical marketing manager for TechInsights.

Intel vient de s'associer avec Silicon Hive, une filiale de Philips spécialisée dans la fabrication de SoC. Disposant de 65 employés, le fondeur devrait utiliser ses talents pour optimiser ses offres Atom et mieux rivaliser avec les puces ARM.

Silicon Hive est connu pour ses puces multimédias destinées aux smartphones et il est facile d'imaginer qu'Intel pourra profiter de son savoir-faire alors qu'il tente désespérément de rivaliser sur ce marché qui lui échappe. Le communiqué n'y va d'ailleurs pas par quatre chemins et parle d'intégrer les technologies de traitement parallèles (comprendre moteur graphique et multimédia) de Silicon Hive dans des SoC Atom.

La stratégie de Santa Clara est relativement simple. Après le rachat de la division mobile d'Infineon, il s'associe avec une société qu'il connait bien puisqu'il avait déjà investi lourdement dans Silicon Hive. Il souhaite donc puiser dans les entreprises qui sont déjà dans le marché des smartphones afin de sortir une puce à succès. Reste à voir si cette tactique lui réussira.

Les termes de ce nouvel accord restent inconnus.