TSMC to Start 20nm Risk Production in 2012
[04/13/2010 12:59 PM]
by Anton Shilov
 
In a bid to offer the most advanced fabrication process technology among contract semiconductor manufacturers, Taiwan Semiconductor Manufacturing Company has decided to skip development of 22nm manufacturing process and move straight to 20nm process technology already in the second half of 2012 with risk production, which results into volume manufacturing in 2013.
 
The technology will be based on a planar process with enhanced high-K metal gate (HKMG), novel strained silicon, and low-resistance copper ultra-low-K interconnects. The technical rationale behind the move is based on the capability of innovative patterning technology and layout design methodologies required at these advanced technology nodes.  
 
During his address to nearly 1.5 thousand TSMC customers and third party alliances, Dr. Shang-yi Chiang, TSMC senior vice president of research and development, said that the move to 20nm creates a superior gate density and chip performance to cost ratio than a 22nm process technology and makes it a more viable platform for advanced technology designers. He also announced that TSMC is expected to enter 20nm risk production in the second half of 2012. Dr. Chiang also indicated that the company has demonstrated record-setting feasibility of other transistor structures such as FinFET and high-mobility devices.
 
"We have reached a point in advanced technology development where we need to be actively concerned about the ROI of advanced technology.  We also need to broaden our thinking beyond the process technology barriers that are inherent in every new node. Collaborative and co-optimized innovation is required to overcome the technological and economic challenges,” said Dr. Chiang.
 
TSMC recently decided to cancel development of 32nm manufacturing process and develop 28nm HKMG fabrication technology instead. Even though the move is projected to improve the company’s competitive position in 2011, the decision comes after the company failed to deliver sufficient production yields with 40nm process technology, which was designed after TSMC decided to skip 45nm production tech.

Taiwan Semiconductor Manufacturing Company (TSMC) will be part of the industry's drive in the development of wafer manufacturing processes below 14nm, according to company chairman and CEO Morris Chang. TSMC has set an ambitious target of US$4.8 billion in capex for 2010, and will increase its workforce to 29,000 from 20,000 in 2009, said Chang.
 
Chang indicated that the global semiconductor market will only see moderate growth from 2011-14 because of a number of reasons, one of which is a slowdown in the pace as defined by Moore's Law.
 
But according to Moore's Law, the 20nm generation will soon arrive, and the next geometry node will also come in the foreseeable future, Chang said. Chang said TSMC's process transition to 10nm may not take place during his tenure, but the company will do its best to move to the next levels.
 
TSMC has to spend more on R&D to cope with the challenge of Moore's Law as well as the rising costs of new manufacturing tools, Chang indicated. It has also stepped up its headhunting efforts, he added.
 
Chang also noted that TSMC's estimates for the global chip market in 2010 and 2011 remain unchanged. The overall chip sector is poised for a 22% growth in 2010 after two years of decline. Following the rebound, the sector will grow by 7% in 2011.
 
Chang made the remarks at a recent company technology forum in San Jose, the US.

Lors de l'Intel Developer Forum de 2009, le constructeur américain avait présenté le Light Peak, une nouvelle technologie de transfert de données entre deux périphériques utilisant la fibre optique.
 
Le principal atout du Light Peak réside dans le débit de transfert annoncé, à savoir 10 gigabits par seconde, soit le double de l'USB 3.0. La technologie est également capable de gérer simultanément plusieurs normes telles que le FireWire, le DisplayPort, l'USB, le SATA ou encore l'Ethernet : son utilisation permettrait donc de réduire drastiquement les différents types de câbles utilisés sur les ordinateurs.
 
Intel a annoncé hier, lors de l'édition 2010 de l'IDF, que le Light Peak sera disponible dès l'an prochain sur le marché. Le fabricant l'annonce comme une alternative à l'USB 3.0, mais nourrit des ambitions plus conséquentes pour son nouveau bébé : « Nous considérons le Light Peak comme le futur successeur logique de l'USB 3.0 » a expliqué Kevin Kahn, l'un des responsables de la société. « Nous aimerions vous proposer le dernier type de câble que vous aurez à utiliser ». Des propos quelques peu ironiques puisqu'Intel avait vainement tenté d'imposer la fibre optique comme standard à l'époque de l'élaboration de l'USB 3.0. Le constructeur chercherait-il à reprendre ses droits au travers du Light Peak ?
 
En tout cas, avant que cette nouvelle technologie domine le monde, il va falloir en mettre à jour, du matériel...

The plan for 32nm next gen
 
Current Pine-Trail M Atom has a good year and a few months more before it gets replaced by a next generation platform. Pine-Trail platform in mobile world got introduced in first days of Q1 2010 and it should remain the dominant Atom platform at least until the second half of 2011.
 
Intel plans to have qualification silicon samples by Q2 2011 and if all goes well, it should start selling and producing Cedar-Trail M 32nm Atoms in second half of 2011. Of course the same timing applies to the chipset, wireless and the rest of the platform.
 
The company doesn't want to get specific and say it will happen in Q3 or Q4 2011 as it wants to leave some space for possible delays, but at least you can have some rough estimates when this new Atom might launch.
 
Don't forget that Cedar Trail –M will come with new Atom CPU in 32nm and full HD support from Intel, so it is cool to get excited about it.

NXP vient d’annoncer avoir livré les premiers exemplaires de test du plus petit micro-contrôleur ARM 32-bit au monde, il s’agit du LPC1102.
 
Un micro-contrôleur plus petit pour du code réduit
 

 
Utilisant un processeur Cortex-M0, le contrôleur repose sur un PCB de 5 mm². L’avantage d’un processeur 32 bits est la possibilité de réduire la taille du code par rapport aux applications 8/16 bits. Intégrant 32 Ko de mémoire Flash et 8 Ko de RAM, le die a une épaisseur de 0,6 mm.
Vers une miniaturisation de nos produits
 
Destiné au marché de l’embarqué, on imagine qu’il sera utilisé pour contrôler des écrans LCD par exemple. Le but est de pouvoir offrir une solution qui permet de réduire l'espace que demande le PCB et qui est aujourd’hui un des facteurs limitant la miniaturisation des produits électroniques. La production en masse devrait commencer durant le dernier trimestre de cette année.

Globalfoundries, the contract maker of semiconductors controlled by Advanced Technology Investment Company and Advanced Micro Devices, has reportedly requested additional incentives from the local government so that to boost room floor of its fab 2 in Luther Forest, New York, in an attempt to expand the clean room space, something that ultimately boosts manufacturing capacity.
 
Globalfoundries proposes to expand the main fab building from 325 586 square feet to 491 054 square feet (30 247 square meters to 45 620 square meters so that it will have the room to potentially expand the clean room where manufacturing takes place from 210 000 square feet to 300 000 square feet (19 509 square meters to 27 870 square meters), reports Times Union web-site.
 
According to the media report, Globalfoundries asks the state to provide incentive of $300 million to boost capacity the fab, which already costs over $4.2 billion.
 
The expansion of clean room will allow Globalfoundries to ultimately increase capacity of the whole Fab 2, which is among the most advanced and largest semiconductor manufacturing facilities in the world. The media report claims that Globalfoundries had been intending all along to potentially expand the clean room to that size, and the zoning changes it requested from the town two years ago set the limit at 300 000 square feet because the company knew all along that it might need the additional capacity.

Globalfoundries, the contract maker of semiconductors controlled by Advanced Technology Investment Company and Advanced Micro Devices, said that it would develop 20nm process technology, along with 22nm fabrication process. Besides, the company indicated that the so-called half-node process technologies would continue to exist, despite of the recent trends.
 
Recently Taiwan Semiconductor Manufacturing Company announced plans to skip 22nm process technology and to move straight to 20nm instead. In addition, both leading contract makers of semiconductors – Globalfoundries and TSMC – decided to skip 32nm bulk process technologies. While Globalfoundries has done this because of certain business reasons, TSMC had too many problems with 40nm to use the same materials and design with 32nm. Previously, almost everyone in the foundry industry have introduced so-called half-node processes, e.g. 55nm, which was a derivative of the 65nm. Although these practices show that full-node processes are losing importance, Globalfoundries claims that going forward both half-node and full-node process technologies will co-exist.
20nm Incoming from Globafoundries
 
For Globalfoundries there are two businesses: manufacturing of AMD’s leading-edge microprocessors and production of more simplistic chips, hence, the company by definition has to invest into a number of process technologies.
 
“We are investing in both the 22nm and 20nm nodes. While half-nodes are certainly becoming an increasing trend there is still high-volume segments like the microprocessor business that require full node transitions,” said Jon Carvill, the director of corporate communications at Globalfoundries.    
 
In theory, it is logical to assume that transition from 28nm to 22nm process technology will make less economic sense than transition from 40nm to 28nm. However, jumping directly from 28nm to 20nm essentially kills 16nm fabrication process. Not that simple, says Globalfoundries.
 
“It is too early to tell on the exact performance/power efficiency benefits transition from 28nm to 22nm/20nm node will yield. As the geometries get smaller so will the levels of the shrinks. That doesn’t necessarily mean there won’t be benefits as or more compelling then what we’ve seen in previous generations,” said Mr. Carvill.
 
In fact, even in the world of bulk chips both full-node processes and half-node processes will co-exist.
 
“We don’t see that happening imminently as high volume processor designers like AMD and Intel continue to develop on both full node and half node technology,” said the Globalfoundries spokesman.
Fewer Semiconductor Manufacturers to Survive
 
Development of leading-edge manufacturing processes costs hundreds of millions, if not billions, as a result, every new node essentially throws out a smaller semiconductor maker from the market.    
 
“Staying on the leading-edge for process technology will present increasing challenges in the marketplace both in cost and complexity. Technology development for a new leading-edge node is now in the billion dollar plus range, new fabs [cost] well in excess of $4 billion. Those costs will be prohibiting for many companies in the marketplace and have the potential to cause further consolidation as well an increased exit in the in-house IDM model of manufacturing,” said Jon Carvill.

Taiwan Semiconductor Manufacturing Company admitted that the economic crisis and inability to get massive financial support from financial institutions under attractive terms would delay the launch of semiconductor manufacturing facilities that process 450mm wafers by several years. At present TSMC expects first 450mm fabs to emerge towards “the middle of the decade”, sometime around the year 2015.
 
"I believe [transition to 450mm wafers] is going to happen, the device manufacturers and governments all have to pitch in and contribute to the effort. People will find a way to invest so that we can deliver 450mm. […] Before the credit crunch, the target [for transition start] was 2012. It has moved out a couple of years, it has pushed out to the middle of this decade,” said  Jack Sun, chief technology officer of TSMC at the International Electronics Forum 2010, reports Electronics Weekly web-site.
 
Back in mid-2008 Intel Corp., Samsung Electronics and TSMC announced that they had reached agreement on the need for industry-wide collaboration to target a transition to 450mm-sized wafers starting in 2012. The companies planned to cooperate with the semiconductor industry to help ensure that all of the required components, infrastructure and capability were developed and tested for a pilot line by the target date. Still, TSMC stressed already in 2008 that there were no actual plans to build a 450mm fab.
 
450mm wafer foundries are projected to cost much more than conventional 300mm fabs, which cost can already be as high as $4.2 billion. The next-generation semiconductor manufacturing facilities will require new buildings along with new equipment across the industry, hence, the transition if projected to be extremely expensive.
 
TSMC said that it had taken delivery of a pre-production EUV tool which it will use for research and development. The company is looking at 2013 – 2014 for production on EUV.
 
There are doubts that 450mm wafer fabs are actually needed in the foreseeable future. Many companies, including Globalfoundries, are working hard to improve efficiency of manufacturing using 300mm fabs and even TSMC, which plans to establish a new 300mm plant that will cost $3.1 billion this year, is implementing measures to streamline processing of 300mm wafers.

Globalfoundries, a contract maker of semiconductors controlled by Advanced Technology Investment Company and Advanced Micro Devices, said that it would announce expansions of its manufacturing capacities assigned for advanced process technologies (130nm and newer) and those expansions are projected to allow the company to compete against arch-rival TSMC’s in terms of 300mm fab capacities.
 
(...)

Globalfoundries was established just over a year ago, but thanks to financial resources of Advanced Technology Investment Company and intellectual property inherited from AMD and its partners, such as IBM, the company is now the world’s third largest contract maker of semiconductors with the world’s most advanced process technologies. The firm said many times that it is on acquisition spree and an analyst believes that the next target could be IBM’s semi fab.
 
(...)

The emergence of Globalfoundries could be one of the most significant events in recent semiconductor history, an analyst said. While for Advanced Micro Devices the creation of Globalfoundries resulted in cost savings only, for Advanced Technology Investment Company it is the chance to create the world’s most powerful contract maker of chips. However, in order to achieve this, Globalfoundries will need to work closely with IBM and adopt its chip design tools.
 
Last week it was reported that Globalfoundries could acquire semiconductor manufacturing operations from IBM, which would provide it additional clients, manufacturing capacities and, perhaps, certain intellectual property. But while it is crucial for Globalfoundries to boost its advanced manufacturing capacities so to be able to compete against Taiwan Semiconductor Manufacturing Company already in the mid-term future, for long-term success it is very important for Globalfoundries to collaborate with IBM in general and adopt/deploy IBM chip design tool-systems, which would give Globalfoundries a decisive competitive advantage in 20nm, 14nm, and finer nodes, according to Boris Petrov, managing partner of the Petrov Group.
 
“IBM will maintain its integrated circuit (IC) process technology leadership via research, but the critical business requirement is also that its Common Platform silicon alliance continues to be successful. […] To be successful Globalfoundries would have to meet cost economics that IBM has apparently failed to meet. This evolution stage represents an immense opportunity – if Globalfoundries, jointly with IBM, is able to construct and implement a new and differentiated vision,” Boris Petrov has written in a new column dedicated to Globalfoundries.
IBM Design Approach: When Perfection Means Isolation
 
The three primary areas of concern to an electronic system designer are power, timing, and noise. An optimal design technology addresses them in an integrated manner; such a system approach is the spirit as well as a distinctive differentiation of IBM's chip design approach.
 
“The foundation of IBM’s leadership position in technology-based services is IBM’s focus on automation; in the case of ICs it is IBM’s focus on automation of system-level design processes. Before actual implementation in silicon, IC design entirely resides in software – at the system architecture, modeling, and application levels. Such software-based IC designs and their design tools are among the most complex software ever developed, and their complexity will continue to increase,” said Mr. Petrov.
 
IBM's "abstraction engines” model basic concepts (shapes, timing, other) at such high levels that they are also used in IC-unrelated modeling (financial, materials, biological, other), notes Mr. Petrov. As chip designs become bigger and more complex, such an approach will be more and more compulsory for successful "first-pass" design with billions of transistors in 28nm, 20nm, and finer lithography technology nodes. The recent woes with TSMC’s 40nm and potential issues with 32nm have already cost chip designers millions of dollars, forced TSMC to can its 32nm fabrication process and the virtually the whole industry to reconsider the roadmaps. But nothing is likely to limit demands for higher-performance computing and going forward fabless designers of chips will have to work closely with foundries and the latter will have to concentrate on creation of design tools, which ensure that advanced designs can be made in high volumes and on time.
 
“The chip design factory approach to silicon integration will likely be the cornerstone of the sub-40nm semiconductor industry. In the sub-32nm chip designs, the emphasis decisively shifts away from an individual expertise and tools approach (the “presence of a super-engineer” concept) to a tightly integrated chip design factory approach,” explained the analyst.
 
IBM's IC design focus continues to be on the needs of state-of-the-art technology, still the center of the chip business has moved away from proprietary modeling and toward open systems which are mandatory for adopting third-party intellectual property and creation of third-party chips. Verification flow, making designs manufacturable without having to model down at the transistor level, and power and timing closure in 28nm and finer lithography all present immense new challenges, the analyst stresses. IBM has already expanded and integrated its tool systems with industry standard tools for commodity solutions. Nonetheless, the overall concept remained unchanged: IBM's tool systems continue to be aimed at the leading edge chips and third-party partners maintain and support the older tools.
 
What is important here is that only a handful of companies – including, but not limited to, AMD or IBM itself – require state-of-the-art fabrication process or designs. As a result, for IBM, its focus on perfection means isolation from the volume market. As a consequence, despite its advantage in design systems, IBM has had limited success outside internal use.
From Extreme to Mainstream
 
The mainstream merchant market's cost and IBM's profitability margin requirements are too far apart, therefore, it is unlikely that IBM will put much more efforts into development of its foundry business. IBM's cost structure and focus on its own demands often make IBM the IC design partner of last choice: a client selects and pays for IBM services because it has nowhere else to turn and since IBM provides an expensive guarantee of on-time delivery of differentiated chips.
 
On the other hand, the chips that contain billions of transistors and considered “extreme” today will become mainstream tomorrow and companies developing them will have to use chip design tools that not only support such complexity, but ensure their low power consumption and introduction on time. Complex devices – such as central processing units or graphics processing units – tend to increase their transistor counts rather rapidly and in less than ten years time there will be chips containing tens of billions of transistors. Needless to say that Globalfoundries and other contract manufacturers will have to provide tools to develop chips of that complexity and potential acquisition, adoption, and deployment of IBM’s chip design expertise and suite of IC design tool-systems will be just what the doctor ordered for the company.
 
“The time for full demonstration of the power and superiority of IBM's [chip design] approach is perhaps ahead. Perhaps, it will be the only approach possible in advanced lithography, with ICs with tens of billions transistors,” said Mr. Petrov.
 
In case the analyst is correct, then, if IBM sells its tools to Globalfoundries, the latter may find itself in a much more competitive position in years. Perhaps, with IBM's suite of chip design tool-systems Globalfoundries may become the only contract maker of semiconductors, who can produce state-of-the-art chips with tens of billions of transistors or at least it will be much more ahead of its rivals.
Globalfoundries Should Convert IBM’s Design Tools for Volume Production
 
“To successfully deploy IBM's IC design tool systems and expertise to much larger and rapidly growing segments of the consumer market, Globalfoundries would have to be able take the good and differentiated and to reject the obsolete and gold-plated,” said Boris Petrov.
 
At present Globalfoundries is fighting for manufacturing volumes via expansions of capacities as well high yields of chips made using leading-edge process technologies. But going forward – as chip designs get even more complex whereas mainstream customers will be unable to design them from scratch – Globalfoundries will have to provide complex support along with robust services, which is when/where IBM’s technologies of today will be required. The difficult challenge will be to drop the too expensive technologies and convert immensely valuable technology into fiscal gold.
 
“A key implication of Globalfoundries and the industry's evolution is that chip design is becoming synonymous with an industrial robotic factory. System vendors need tightly integrated chip design and wafer foundry factories. If Globalfoundries is able to obtain, adapt, and cost effectively deploy IBM's chip design capabilities it will have a decisive and sustainable competitive advantage in advanced technology nodes for its foundry customers,” asserts the analyst.

Intel vient de confirmer que les processeurs 22 nm seraient mis sur le marché dans les temps et que la firme travaille déjà sur le 15 nm, le 11 nm et même le 8 nm qui est prévu pour 2017.
Intel rompt avec le pessimisme général
 
Le 22 nm est attendu deux ans après la sortie du 32 nm qui fut mis sur le marché en début d’année, ce qui le place donc en début 2012. Intel a expliqué que l’accroissement de la finesse de gravure rend la fabrication de puces plus complexe, car il demande une multiplication des étapes de production. Ainsi, produire un processeur en 22 nm demande deux fois plus d’étapes qu’un modèle en 90 nm. Malgré cet obstacle, Intel se félicite d’avoir réussi à réduire les temps de développement pour chaque finesse de gravure.
 
La roadmap d’Intel s’étend sur 10 ans et la firme estime qu’il n‘y a pas de raison pour que l’innovation ralentisse. Le 15 nm devrait débarquer en 2013, contre 2015 pour le 11 nm. Même si Intel n’en parle pas explicitement, il semblerait que le 5 nm soit attendu pour 2019. C’est donc un discours très différent de celui d’un nombre important d’analystes et de fondeurs qui adopte souvent un ton alarmiste et affirme qu’il ne sera plus possible d’augmenter la finesse de gravure en raison des limites physiques et des coûts exorbitants des équipements.
Intel a le vent dans le dos
 
Il faut dire qu’Intel jouit d’une position confortable. Contrairement à TSMC, il n’a pas connu de problème de rendement avec ses puces en 40 nm (cf. « TSMC et le 40 nm : les rendements sont faibles »). En plus de profiter de process plus efficaces et performants que ses concurrents, Intel semble avoir trouvé le moyen de rentabiliser ses usines en augmentant leur durée de vie. Le fondeur donne l’exemple de la Fab 11X, dont la construction a commencé en 1999 et qui est utilisée aujourd’hui pour le 32 nm. Intel montre qu’une usine servira d’abord pour ses processeurs, puis ses chipsets et enfin ses processeurs embarqués, rentabilisant les investissements. Cela permet donc à la firme de faire face à une nouvelle tendance économique qui veut que les machines et les wafers perdent plus rapidement de leur valeur en raison des innovations toujours plus rapides.

Les puces Fusion d’AMD, combinant un IGP et un CPU, devraient arriver au début de l’année prochaine, mais nous apprenons que les secondes générations de puces n’arriveront pas avant 2015.
Le CPU et le GPU sans distinction
 
C’est ce qu’a fait comprendre un des vice-présidents de la firme qui a précisé que l’architecture du Fusion 2 sera différente par rapport à ce que l’on connait aujourd’hui. Au lieu d’avoir un die pour le CPU et un die pour le GPU, le tout regroupé dans un même package, les deux seront gravés sur un seul et même die. Selon lui, le processeur pourra gérer les calculs graphiques et les calculs plus généraux, à tel point qu’il sera impossible de distinguer le GPU du CPU.
 
Cela fait partie de la nouvelle idéologie de la firme qui estime que les GPU sont voués à mourir et que les calculs seront pris en charge par les CPU. Sans renoncer au fait que certains calculs sont exécutés plus rapidement sur l’architecture hautement parallèle d’un GPU, il semblerait qu’AMD souhaite fusionner les deux architectures au sein d’une seule et même puce qui prendrait en charge tous les types de calculs.
Des questions et des espoirs
 
Beaucoup de questions restent encore en suspends, une des plus importantes étant de savoir si le Fusion de 2015 pourra faire tourner les applications 3D sans demander une réécriture du code et si les programmes GPGPU pourront utiliser les API existantes. Si on lit entre les lignes, il semblerait que le CPU intègre des unités de calculs similaires à ce que l’on rencontre dans les GPU. Pourquoi pas? À cette date, AMD devrait graver en 15 nm s’il continue de suivre Intel avec quelques années de retard (cf. « Intel parle de son 8 nm ») et le fait qu’il possède ATI lui prodigue le savoir nécessaire. Si l’idée semble prometteuse en théorie, il faut se demander comment AMD concevra le contrôleur en charge d’envoyer le code vers les bonnes unités.
 
Au final, on ne peut s’empêcher de penser qu’AMD avance vers une forme de GPGPU. La firme a déjà dit que certaines applications, comme les antivirus, profiteraient d’une architecture GPU. En l’intégrant dans le CPU, on imagine qu’il sera plus facile de tirer parti du parallélisme offert par ces puces. Voici une grande promesse et beaucoup d’espoir. AMD a maintenant cinq ans pour trouver la bonne solution.

Advanced Micro Devices plans to finally launch its hybrid chips – which feature x86 central processing along with graphics processing cores – code-named Fusion in early 2011, however, according to a vice president of AMD, the second iteration of Fusion processors will not only be heterogeneous in terms of different cores within one piece of silicon, but the cores themselves will process both graphics and general-purpose data.
 
“The first iteration of Fusion will include a CPU and GPU, but by 2015 the model could change. In the second iteration [in] 2015, you are not going to be able to tell the difference. It's all going away," said Leslie Sobon, vice president of marketing at AMD, reports IDG News agency.
 
The Fusion concept was born back in 2006, when AMD acquired ATI Technologies, a leading supplier of graphics and multimedia chips. The company began talking about actual plans to integrate central processing unit (CPUs) with graphics processing unit (GPU) initially after the transaction and initially aimed 2008 – 2009 timeframe for Fusion chips. However, for a number of times AMD had to delay the actual products. Nevertheless, in 2011 the world’s second largest designer of microprocessors intends to launch two models of CPU-GPU chips: Llano, which is based on AMD Phenom II and ATI Radeon HD 5000 graphics cores, as well as Ontario, which is powered by Bobcat micro-architecture x86 cores as well as DirectX 11 graphics cores.
 
Quite interestingly, after AMD acquired ATI, the CPU designer said that eventually special purpose graphics processors would not be needed and would become obsolete, just like discrete math-coprocessors (or floating point units [FPUs]) did back in the late eighties and early nineties. Although AMD is successfully developing and selling its ATI Radeon graphics family and the first Fusion chips will have separate GPU core within one piece of silicon, it looks like the company still has plans to unify CPU and GPU cores going forward.
 
Nevertheless, AMD admits that many relatively simplistic GPU cores can process certain types of data faster than traditional x86 CPU cores, which is why modern graphics processors can improve user experience not only in video games.
 
"The GPU is perfect for antivirus. It's a perfect parallel-processed application. In the Fusion-based time frame that's where it needs to go," Ms. Sobon is reported to have said.

Des scientifiques chinois viennent de montrer qu'il est possible de transférer des données à 2 mégabits/s en utilisant de simples lampes à LED. Ils ont en fait intégré un système permettant de faire scintiller les LED à très haute fréquence — de façon invisible pour l'oeil humain — pour transmettre des données en modulant la fréquence du scintillement. Le système à l'avantage d'être omnidirectionnel, ce qui permet d'offrir une connexion à plusieurs appareils simultanément, et peut être intégré facilement dans un plafond. Sans offrir la vitesse du Wi-Fi ou du CPL (et encore moins de l'Ethernet), cette solution a l'avantage d'être simple à intégrer et pourrait même — à terme — être utilisée dans un écran, au niveau du rétroéclairage.
 
Reste à voir si cette technologie, initiée par le Boston University’s College of Engineering il y a presque deux ans (cf. La lumière pour remplacer le Wi-Fi), sera intégrée dans nos ordinateurs ou si elle se cantonnera (à cause de sa vitesse limitée) à des usages alternatifs comme « l'Internet des objets ».

The modern trend of microprocessors’ development is focused around creation of devices with as many cores as possible. However, there are algorithms that cannot benefit from many-core architectures or multi-threading execution. In order to boost performance of single-threaded applications on multi-core microprocessors, Intel Corp. recently outlined the technology called “Anaphase”.
 
Researchers from Intel Labs Barcelona have developed “Anaphase” technology, which is a novel hardware/software hybrid approach to leverage multiple cores in order to improve single-thread performance on multi-core processors. This research focuses on different speculative techniques to automatically partition single thread applications to be processed on multiple cores.
 
The proposed technique features a set of novel hardware mechanisms that support the execution of threads generated at compile time. These threads result from a fine-grain speculative decomposition of the original application and they are executed under a modified multi-core system that includes: mechanisms to support multiple versions; mechanisms to detect violations among threads; mechanisms to reconstruct the original sequential order; and mechanisms to checkpoint the architectural state and recovery to handle misspeculations. On the hardware side, a new unit called “Inter-Core Memory Coherency Module” (ICMC) could be integrated into the die of future processors.
 
According to Intel, the proposed hardware/software scheme outperforms previous hardware-only schemes to implement the idea of combining cores for executing single-thread applications in a multi-core design by more than 10% on average on Spec2006 for all configurations. Moreover, single-thread performance is improved by 41% on average when the proposed scheme is used on a so-called “tiny-core” (Intel did not reveal, what tiny-core actually is, but it may potentially be a part of the company’s SSC 48-core processor), and up to 2.6 times for some selected applications.
 
At the present Anaphase is a research project and the Intel Labs Barcelona researchers are looking into ways how to potentially integrate this technology into future processor designs.
 
Considering that Intel is working on numerous many-core designs, including Larrabee x86 graphics processor and 48-core supercomputer on a chip (SCC) prototype, the ICMC may indeed be a useful piece of hardware. In fact, not only for Intel. Both ATI, graphics business unit of Advanced Micro Devices, and Nvidia Corp. are working hard to implement their many-core graphics processing units (GPUs) into various high-performance computing (HPC) segments. Although raw horsepower is more important for HPC that performance of single-threaded apps, as general purpose processing on GPUs (GPGPU) becomes more popular on different markets, hardware/software tricks to speed up single-threaded algorithms may become necessary.

United Microelectronics Corp., the world’s second largest contract maker of semiconductors, on Thursday celebrated its 30th anniversary and proclaimed plans for the foreseeable future. At the moment UMC is working on 28nm and 20nm process technologies as well as is preparing its new 300mm fab, which will help the firm to boost the output of advanced chips.
 
“Currently, UMC has a total of 10 fabs continuously operating around the world, in Hsinchu, Tainan, Japan, and Singapore. In the earliest days from 30 years ago, UMC started with the manufacture of electronic watch ICs; now, we offer the most advanced 40nm volume production technologies. With our 10 fabs around the world providing global customers with the most comprehensive foundry solutions covering computing, consumer, and communications applications,” said Stan Hung, the chairman of UMC.
 
Since the debut of UMC's first 300mm fab 12A-in the Southern Taiwan Science Park in November 1999, UMC has operated in the Southern Taiwan Science Park for over 10 years. Fab12A began production in 2001 and can now produce chips at 65nm, 45nm and 40nm nodes. In response to increasing demands from customers for advanced process capacity, UMC has constructed buildings for phases 3 and 4 next to the original phases 1 and 2 of the fab 12A. At present the Fab 12A has capacity of 36 thousand 300mm wafers a month, or 432 thousand of 300mm wafers per annum. Once the phases 3 and 4 of the fab 12A become fully operational, the total capacity of the whole fab is projected to be over a million of 300mm wafers per annum, or more than 83 thousand wafers per months. UMC also operates fab 12i in Singapore, which also processes 300mm wafers, that has monthly capacity of around 45 million wafers.
 
"On the day we celebrate our 30th anniversary, we also simultaneously kick-off Fab12A's phases 3 and 4 in the Southern Taiwan Science Park. At the fab, we are now setting up the cleanroom facilities and installing the industry's most advanced automation and manufacturing systems. Upon completion, Fab12A's annual capacity is estimated to reach over one million of 300mm  wafers,” said Dr. Shih-Wei Sun, chief executive officer of UMC.
 
UMC at present plans to start risk production of chips using 28nm using gate-last high-K/metal gate (HKMG) technology by the end of 2010. Early this year, UMC also began working with customers on planning and initial development of advanced 20nm technology.
 
In 2004 UMC moved its research and development headquarters to Tainan and built it next to its 300mm fab to enable close collaboration between advanced technology development and the subsequent manufacturing so to accelerate ramp-up to volume production. Tainan is currently home to 2600 employees, 500 of which are R&D engineers.

Il mesure 30 micromètres de longueur, 8 micromètres de hauteur, sa longueur d'onde est de 200 micromètres: il s'agit non seulement du plus petit laser à pompage électrique du monde, mais aussi du premier à être plus petit que la longueur d'onde de la lumière qu'il émet! Cet exploit, réalisé par des chercheurs de l'Ecole polytechnique fédérale de Zurich, repousse les limites en matière de technologie laser. Avec des lasers classiques (émettant de la lumière amplifiée), on peut déjà lire des DVD, scanner des codes-barres ou corriger des défauts de vision. Ils fonctionnent avec un amplificateur optique (pour le signal lumineux) et une cavité, appelée résonateur optique, constituée de deux miroirs, qui permet à la lumière de passer plusieurs fois dans le milieu amplificateur. Problème: les miroirs du résonateur doivent forcément être plus grands que la longueur d'onde de la lumière émise, ce qui limite la taille des lasers. Pour contourner cet obstacle, les chercheurs suisses ont eu une idée originale: remplacer le résonateur optique par un modèle électrique composé d'une bobine et de deux condensateurs. Résultat: la taille du résonateur n'est plus imposée par la longueur d'onde de la lumière. Cette miniaturisation ouvre des perspectives inouïes, notamment pour les fabriquants de puces. De quoi faire entrer la lumière dans nos ordinateurs et accélérer l'échange de données sur les microprocesseurs.

If the new atomic transistor can be made in large numbers it could mean chips with components up to 100 times smaller than on existing processors.

A transistor-based light source would switch much faster than a diode, and because of its planar design it could be more easily integrated onto computer chips, providing faster data transmission across chips than copper wire, says Michele Muccini, who heads a research unit at the Institute for Nanostructured Materials, part of the National Research Council in Bologna, Italy. ...  When light travels through the diode's contacts (OLED), there is usually a loss of efficiency of 20 to 30 percent, Muccini says, a loss the transistor (OLET) does not suffer.

Globalfoundries, a contract maker of semiconductors controlled by Advanced Technology Investment Company and Advanced Micro Devices, on Tuesday announced major plans to expand its manufacturing capacities. When the expanded fabs become fully operational, Globalfoundries may easily become the world’s largest manufacturer of advanced chips, which are made on 300mm wafers.
 
190 Thousand 300mm Wafers Per Month in 2013
 
At the company's leading-edge Dresden manufacturing campus, Fab 1, the expansion focus will be on adding new capacity to support additional growth opportunities for 45/40/28nm technologies as well as initial 22nm development. This expansion will see a new facility constructed at Fab 1 that will add nearly 110 thousand square feet of clean room space to enable the site to scale output up to 80 thousand wafers per month over the next two years. The largest wafer fab in Europe, Fab 1's leading-edge wafer fabrication equipment will cover an area equivalent to approximately eight soccer fields. The first output from this new expansion is expected in 2011 with construction work planned to start immediately. The start of this expansion project at Fab 1 is, however, still subject to the approval of a state aid package by the German authorities and the European Commission.
 
To support long-term growth at the 22/20nm generation, Globalfoundries plans to expand Fab 8, the company's new leading-edge fab currently under construction at the Luther Forest Technology Campus in Saratoga County, New York. The expansion will increase the size of the cleanroom shell by approximately 90 thousand square feet, bringing the total available cleanroom space to approximately 300 thousand square feet, equivalent to roughly six soccer fields of state-of-the-art wafer fabrication equipment. Work on the shell expansion is expected to begin later this month pending final approval of an investment agreement with Empire State Development Corporation and the State of New York. The total facility, including cleanroom support infrastructure and office space, includes more than 1.3 million square feet of space and is expected to come online in 2012 with volume production targeted for early 2013. The larger cleanroom would allow for the future fit-up and equipment necessary to enable a total output of approximately 60 thousand wafers per month once fully ramped.
 
In addition to new expansion initiatives in Dresden and New York, Globalfoundries also is continuing with its previously announced expansion at Fab 7 in Singapore to reach an output level of 50 thousand wafers per month, an increase of nearly 50% from current levels. During the expansion, Fab 7 will continue to focus on manufacturing technologies ranging from the 65nm to 40nm technology nodes.
 
When the new expanded fab become fully operational, total Globalfoundries’ 300mm output will be around 190 thousand wafers per month. By contrast, the planned 300mm capacities of Taiwan Semiconductor Manufacturing Company and United Microelectronics Corp. are 100 thousand (plus one fab with unknown capacities) and 128 thousand wafers, respectively.
 
ATIC Establishes High-Tech Zone in Abu Dhabi
 
In addition to the capacity expansion projects at Fab 1 and Fab 8, ATIC announced initial plans for the creation of an advanced technology cluster in Abu Dhabi. The site, adjacent to Abu Dhabi International Airport and measuring three square kilometers in size, is ideally suited to house a future advanced technology cluster in the region with close proximity to regional transportation hubs and physical infrastructure. Globalfoundries is committed to partnering with ATIC to share best practices and expertise in cluster creation in the near-term and putting a significant technology and manufacturing presence in the region long term. The goal for the site is to be the Middle Eastern hub of a global technology and manufacturing network to support the long-term deployment of capital for ATIC portfolio companies, in capital-intensive advanced technologies.
 
"The formation of the new Globalfoundries was predicated on creating a world-class technology and manufacturing company that had the scale and resources to compete for industry leadership in this capital intensive market. For ATIC, this also represented the first step in Abu Dhabi's vision to become a leader in the semiconductor industry. Today we announce the next phase as we take our first steps in establishing a world-class advanced technology cluster over the coming years. We look forward to working with the Globalfoundries team to leverage the collective successes of Singapore, Dresden and New York as we create the industry's next innovation cluster in Abu Dhabi,” said Ibrahim Ajami, chief executive officer of ATIC.

Intel® Many Integrated Core Chips to Extend Intel's Role in Accelerating Science and Discovery
 
NEWS HIGHLIGHTS
 
    * The first product codenamed "Knights Corner" will target Intel's 22nm process and use Moore's Law to scale to more than 50 Intel cores.
    * Intel® Xeon® processors and Intel® Many Integrated Core architecture-based products to share common tools, software algorithms and programming techniques.
    * Products build upon Intel's history of many-core related research including Intel's "Larrabee" program and Single-chip Cloud Computer.
    * The share of the TOP500 list that features Intel processors grows to 408 systems, nearly 82 percent.
 
 
 
SANTA CLARA, Calif. and HAMBURG, Germany, May 31, 2010 - During the International Supercomputing Conference (ISC), Intel Corporation announced plans to deliver new products based on the Intel® Many Integrated Core (MIC) architecture that will create platforms running at trillions of calculations per second, while also retaining the benefits of standard Intel processors.
 
Targeting high-performance computing segments such as exploration, scientific research and financial or climate simulation, the first product, codenamed "Knights Corner," will be made on Intel's 22-nanometer manufacturing (nm) process – using transistor structures as small as 22 billionths of a meter – and will use Moore's Law to scale to more than 50 Intel processing cores on a single chip. While the vast majority of workloads will still run best on award-winning Intel® Xeon® processors, Intel® MIC architecture will help accelerate select highly parallel applications.
 
Industry design and development kits codenamed "Knights Ferry" are currently shipping to select developers, and beginning in the second half of 2010, Intel will expand the program to deliver an extensive range of developer tools for Intel MIC architecture. Common Intel software tools and optimization techniques between Intel MIC architecture and Intel Xeon processors will support diverse programming models that will place unprecedented performance in the hands of scientists, researchers and engineers, allowing them to increase their pace of discovery and preserve their existing software investments. The Intel® MIC architecture is derived from several Intel projects, including "Larrabee" and such Intel Labs research projects as the Single-chip Cloud Computer.
 
"The CERN openlab team was able to migrate a complex C++ parallel benchmark to the Intel MIC software development platform in just a few days," said Sverre Jarp, CTO of CERN openlab. "The familiar hardware programming model allowed us to get the software running much faster than expected."
 
"Intel's Xeon processors, and now our new Intel® Many Integrated Core architecture products, will further push the boundaries of science and discovery as Intel accelerates solutions to some of humanity's most challenging problems," said Kirk Skaugen, vice president and general manager of Intel's Data Center Group. "The Intel® MIC architecture will extend Intel's leading HPC products and solutions that are already in nearly 82 percent of the world's top supercomputers. Today's investments are indicative of Intel's growing commitment to the global HPC community."
 
TOP500
The 35th edition of the TOP500 list, which was announced at ISC, shows that Intel continues to be the platform of choice in high-performance computing, with 408 systems, or nearly 82 percent, powered by Intel processors. More than 90 percent of quad-core-based systems use Intel processors, with the Intel® Xeon® 5500 series processor nearly doubling its presence with 186 systems. Intel chips also power three systems in the top 10, and four out of five new entrants in the top 30. Seven systems contain the recently announced Intel® Xeon® 5600 series processor, codenamed "Westmere-EP," and two systems are powered by the new Intel® Xeon® 7500 series processor, codenamed "Nehalem-EX."
 
The Intel Xeon processor 5600 series is playing the vital role in the highest-ranked system from China in the history of the Top500. The No. 2 system, located at the National Supercomputing Center (NSCS) in Shenzhen, reached 1.2 petaflops on the Linpack benchmark with a Dawning TC3600*. NSCS is a hub for research and innovation in China.
 
The semi-annual TOP500 list of supercomputers is the work of Hans Meuer of the University of Mannheim, Erich Strohmaier and Horst Simon of the U.S. Department of Energy's National Energy Research Scientific Computing Center, and Jack Dongarra of the University of Tennessee. The complete report is available at www.top500.org.
 
New Exascale Lab
To meet the growing challenge of running large-scale simulations in the multi petaflops and exaflops range of computing, Intel, Forschungszentrum Julich (FZJ) and ParTec will announce a multi-year commitment to create the ExaCluster Laboratory (ECL) at Julich. The lab will develop key technologies, tools and methods to power multi petaflops and exaflops machines, focusing on the scalability and resilience of those systems. ECL will become the latest member of Intel Labs Europe, a network of research and innovation centers spanning Europe.

Elpida vient d’annoncer qu’il allait commencer la production en masse de puces DRAM haute capacité utilisant les technologies TSV, grâce aux équipements installés dans ses usines l’année dernière.
 
Elpida perfectionne son TSV
 
Les prototypes utilisent 8 couches de DRAM de 1 Gbit et des modèles utilisant des couches de 2 Gbits pour un total de 16 Gbits devraient arriver cette année. La firme commence avec des puces mémoires car elles sont relativement simple à fabriquer, mais elle devrait utiliser le TSV pour des chips plus complexes d’ici 2011 et 2012.
 
Vers la démocratisation des architectures 3D
 
Pour rappel, le TSV, ou Through Silicon Via, désigne une connexion électrique verticale traversant complètement le die. Un laser troue les puces verticalement et un câblage de cuivre permet de relier les puces entre elles directement. C’est une technologie fondamentale pour la création de package 3D.

MSI devrait commencer à livrer des cartes UEFI d’ici la fin de l’année et complètement abandonner le BIOS d’ici trois ans.
 
La mort annoncée du BIOS chez MSI
 
C’est ce que rapportent nos confrères de ThinkQ qui citent des sources travaillant pour MSI. Les premiers produits UEFI seront des cartes mères Sandy Bridge. Le détail intéressant est que la firme ne se limitera pas aux modèles haut de gamme, comme certains de ses concurrents, mais qu’il apportera cette technologie sur tous les segments utilisant la prochaine plateforme d’Intel. Les premiers modèles devraient débarquer fin 2010, début 2011.
 
Il y a maintenant une raison pour passer à l’UEFI
 
Ce n’est pas la première fois qu’un fabricant de cartes mères, ni même MSI, commercialise des cartes UEFI, ce dernier ayant mis des modèles P45 sur le marché en 2008 équipés de ce qu’il appelle « ClickBIOS » en référence au fait que le programme utilise la souris, contrairement au BIOS classique (« Cartes mères MSI et EFI »). Néanmoins, l’annonce de disques durs de 3 To (cf. « Seagate promet un disque dur 3 To ») nécessitant une carte mère UEFI (cf. « Comment va se gérer la limite des 2 Tio »), a poussé le Taïwanais à faire le grand saut tant attendu.
 
En effet, cela fait maintenant un moment que l’on espère cette transition par les fabricants (cf. « Les PC adopteront enfin l'EFI en 2008 ? »), mais la crise et le fait qu’ils n’avaient pas réellement de raison technologique pour abandonner le BIOS ont motivé les acteurs à repousser cette mesure. Il faut dire qu’un UEFI reste toujours plus cher à concevoir qu’un BIOS et qu’il est moins facile de l’intégrer dans la carte mère en raison d’un code plus large et de la nécessité d’adapter le programme aux divers modèles de cartes mères.

(...)
 
Today at DAC 2010, ARM announced the delivery of the industry’s first complete vertically optimized 32/28 nanometer [nm] design platform. The solution consists of optimized high performance, low-power processor and physical IP from ARM; tool enablement connectivity IP and integrated design flow from Synopsys; and 32/28nm low-power process technology from the Common Platform alliance [PDF Download] of IBM, Samsung and GlobalFoundries.
 
The Common Platform 32/28nm process uses an innovative HKMG [high-k metal gate] approach to address the limitations of polysilicon technology. It leverages the research and development efforts of the IBM joint technology development alliance to offer a high-performance, low-power manufacturing platform. The 32nm technology is scalable to 28nm for area optimization. Clients can seamlessly transition to 28nm technology without the need for a major redesign and with lower risk, reduced cost, and faster time-to-market. All physical IP are readily accessible on DesignStart.
 
Ten test chips were produced through the three-way collaboration in 32 and 28nm HKMG process technology. Producing these chips has helped validate the design platform, including PDKs, Physical IP, Cortex processors, Interface IP and core tool enablement and design methodology for accelerating first customer silicon success.
 
The Samsung factory qualified the 32nm LP [low power] HKMG process technology. The qualified technology provides a 20 percent performance gain, a 30 percent dynamic power reduction, and a 55 percent reduction in power leakage compared to 45nm.
 
The Common Platform 32/28nm process provides a standardized platform to manufacture 28nm LP HKMG semiconductors for a new generation of mobile devices, The 28nm LP technology with Gate First HKMG will be factory qualified at GlobalFoundries in Q1 2011.
 
(...)

Toshiba vient de développer un transistor 3D pouvant être gravé en 16 nm et utilisant un nanofil de silicium reliant la source et le drain.
 
Les résultats de ces recherches seront présentés durant un colloque qui se tiendra aujourd’hui à Hawaï. C’est la première fois que l’on arrive à obtenir des performances de l’ordre de 1 mA/µm sous tension, avec ce genre de transistor. L’avantage de cette structure est qu’elle limite grandement les fuites de courant.
 
La présence de résistances parasites au niveau de la source et du drain ont néanmoins posé un problème aux scientifiques travaillant sur ce transistor. Pour le pallier, Toshiba a optimisé la méthode de fabrication de la grille, sans donner plus de détail à part pour dire que l’épaisseur des parois passe de 30 nm à 10 nm.

Writing Circuits on Graphene
 
A heated AFM tip can draw nanometers-wide conductive lines on graphene oxide.

Intel va donner des nouvelles de son processeur Terascale durant la conférence VLSI Circuits à Hawaï. Au programme, une amélioration des performances et du rendement.
 
Un processeur qui a du coeur
 
Le single-chip cloud computer (cf. « Le CPU 48 cores d’Intel en démonstration ») est un processeur utilisant une architecture MIC (Many Integrated Core). Il est constitué de 24 processeurs dual core mis côte à côte, chacun disposant de son cache L1 et L2 dont la cohérence est gérée de façon logicielle, ce qui permet aux développeurs de la modifier en fonction de ses besoins. Les 24 CPU communiquent entre eux à l’aide d’un réseau de 256 Go/s pris en charge par 24 routeurs. Intel a récemment livré son SCC à certains de ses partenaires dans le cadre de recherches sur l’optimisation des processeurs multicores et la meilleure exploitation des ressources par les logiciels.
 
Mieux et plus vite
 
Intel va donner une conférence détaillant les améliorations apportées depuis la première présentation de son projet en 2007 (cf. « Intel : un peu plus sur le processeur 80 cores »). Au programme, des temps de latence de routeur à routeur réduits de 40 % et un rendement qui passe à 7,2 Tbits/s et par Watt. Le processeur opère à une tension variant entre 550 mV et 1,25 V et à une fréquence tournant entre 60 MHz et 2,35 GHz. Le premier fruit commercialisable de ces recherches devrait être le Xeon à 50 coeurs connus pour l’instant sous le nom de code de Knight’s Corner.

La Design Automation Conference 2010 a été l’occasion pour GlobalFoundries de présenter ses nouveaux processus de gravure en 32 et 28 nm HKMG. Fruits d’un partenariat entre le fondeur et IBM, Samsung Electronics, ARM ou encore Synopsys, ces procédés de gravure viennent prendre la relève de l’actuelle 45 nm. Si la gravure en 32 nm est véritablement un nouveau process, le 28 nm n’est en réalité qu’une extension du 32 nm. En pratique, cela signifie que le passage du 32 nm vers le 28 nm ne nécessitera pas de restructuration profonde des outils, ce qui permettra de réduire les coûts ainsi que les délais de migration.
 
Dix circuits de test en 32 nm et 28 nm ont été réalisés, tous ont passé les tests physiques. Une fois les problèmes techniques résolus, une gravure plus fine permet pour rappel de réduire la consommation et d’améliorer les performances des puces. La gravure en 32 nm low-power HKMG est actuellement en cours de validation par Samsung. Pour le 28 nm low-power HKMG, il faudra attendre le premier trimestre 2011…