Chez Intel, les CPU Ivy Bridge ne sont pas encore sortis, mais ils semblent déjà être de l'histoire ancienne. Les rumeurs et les fuites se concentrent désormais sur Haswell, l'après Ivy Bridge, prévu pour 2013. Il y a peu on apprenait que les Haswell possèderaient un étage supplémentaire de mémoire cache, un L4. Cette rumeur est confirmée et précisée par nos confrères de Semi Accurate : selon eux cet espace mémoire serait en fait un tampon réservé au GPU de Haswell.

Selon VR-Zone, Intel pourrait adopter la DDR4 dès début 2014 au sein de la plate-forme Haswell-EX. Destinée aux serveurs, cette plate-forme utilisera l'architecture Haswell 22nm qui sera introduite en 2013 sur LGA 1150, mais ira plus loin puisqu'il pourrait y avoir jusqu'à 16 cœurs par Socket, soit un besoin en bande passante énorme.

[...]Now, Intel's going a step further in the Haswell EP and Haswell EX generation: the QPI will be sped up to 9.6 Gbit/s per pin, or 38.4 GByte/s per bidirectional 16-bit link, and also there will be more than just CPU attached to it.[...]

Intel has shared some new details with its notebook partners indicating that Lynx Point, a chipset that matches Haswell CPUs in Shark Bay 2013 platform, has a significantly improved power profile. You should expect 25 percent lower TDP and 50 percent lower average power than Panther Point chipset of Chief River 2012.

With the 14 nm "Broadwell" architecture, Intel will take a new step towards integration of the platform-controller hub (PCH) with the CPU, by designing it to be a multi-chip module (with the CPU+northbridge in one die, and PCH on the other). This would make "Broadwell" a true System-on-chip (SoC), which allows over 90 percent of the system's I/O to be routed to the processor socket, including memory, PCI-Express, SATA, USB, etc. Although not the first to the industry with single-chip chipsets and integrated memory controllers, Intel rapidly reshaped the arrangement between CPU and core-logic, over the past four years.  
 
 It began with transfer of memory controller from northbridge to CPU die (45 nm "Bloomfield" ), and transfer of the entire northbridge to the CPU die (45 nm "Lynnfield" ). The graphics northbridge transferred a little more gradually, first as multi-chip module with a separate CPU die (32 nm "Clarkdale" ), then complete integration with the CPU die (32 nm "Sandy Bridge" ). All through, the southbridge, or I/O controller hub (ICH) remained outside the CPU package, with the addition of a display output logic, it transformed into a "platform controller hub" (PCH), which is still just a glorified southbridge. Naturally then, such a drastic relocation of system components will warrant a socket change.

The real surprise is GT3, which as rumored will consist of four modules, totaling 40 EUS and 160 ALUs (shader processors) and GT3 will also Crystalwell technology (dedicated graphics memory), without a doubt a quantum leap in relation to Intel’s previous IGP, which should provide at least 2.5x performance compared with the current HD Graphics 4000 (GT2) of Ivy Bridge.

 

Intel: Write your first program with Haswell new instructions (blog)
• Getting ready for Haswell on Windows
• Getting ready for Haswell on Linux
• Bit Manipulation
• Running your program without Haswell